DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on 05/05/2025, 12/08/2025, and 09/10/2026 is/are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1, 5, 8-10, 14, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim(s) 1 and 10, recites “a first electrode and a second electrode, configured to apply one or more voltages that reverse-bias the reverse-biased semiconductor junction.” With two electrodes, only a single voltage at a given time can be applied. It is therefore not clear from the claim(s) which features are necessary in order to apply more than a single voltage by means of the two electrodes. Therefore, the scope of claim(s) 1, and 10 are unclear and indefinite.
Regarding Claim(s) 5 and 14, recites “wherein the one or more voltages are set to bias both the forward-biased semiconductor junction and the reverse-biased semiconductor junction.” Only a single voltage at a given time can be set to bias both the forward-biased and reverse-biased semiconductor junctions. It is therefore not clear from the claim(s) which features are necessary in order to apply more than a single voltage to the aforementioned junctions. Additionally, it is unclear from claim(s) 5, and 14 by which features of the device second layers which form a semiconductor junction can be distinguished from “second layers which form a forward-biased semiconductor junction.” Therefore, the scope of claim(s) 5, and 14 are unclear and indefinite.
Regarding Claim(s) 8-9, and 17-18, it is not clear which ones of the mentioned layers belong to the first layers and which ones belong to the second layers. Therefore, the scope of claim(s) 8-9, and 17-18 are unclear and indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-5, 10, 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Adrien Bruno, (hereinafter BRUNO), US 5523557 A, in view of Eitaro Ishimura et al, (hereinafter ISHIMURA), US 20050263787 A1.
Regarding Claim 1, BRUNO teaches an optical communication system (Fig. 9, [Col. 6, Lines 5-15]), comprising:
an optical waveguide (Fig. 9, G2, optical guides) arranged to receive and guide an optical signal (Figs. 4/5, G2, [Col. 4, Lines 15-24]); and
a photodetector (PD) (Figs. 3/4, D1/D2, diodes) configured to receive the optical signal (Figs. 4/5, G2, [Col. 4, Lines 15-24]) from the optical waveguide (Fig. 9, G2, optical guides) and to convert the optical signal into an electrical signal (Figs. 6/7, [Col. 4, Lines 56-65]), the PD comprising (Figs. 3/4, D1/D2, diodes):
a stack of layers (Fig. 5, 24/26/28, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]), comprising at least:
first layers (Fig. 5, 24/262/282, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]) including two or more semiconductor layers forming a reverse-biased semiconductor junction, configured to produce the electrical signal in response to the optical signal impinging thereon (Fig. 4-7, [Col. 4, Lines 56-65]); and
second layers (Fig. 5, 24/261/281, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]) forming a capacitance component that is connected in series with the reverse-biased semiconductor junction (Figs. 5-7, Col. 5, Lines 12-21]); and
a first electrode (Fig. 5, 291, first metallic contact) and a second electrode (Fig. 5, 292, second metallic contact), configured to (i) apply one or more voltages that reverse-bias the reverse-biased semiconductor junction and (ii) output the electrical signal (Figs. 4-7, Col. 4, Lines 9-14; Col. 4, Line 59 - Col. 5, Line 3]).
Though BRUNO teaches that a stack of layers including two or more semiconductor layers forming reverse-biased semiconductor junction and further forming a capacitance that is connected with the reverse-biased semiconductor junction, BRUNO does not explicitly show an optical communication system, comprising a photodetector comprising: a stack of layers, comprising at least: first layers including two or more semiconductor layers forming a reverse-biased semiconductor junction, configured to produce the electrical signal in response to the optical signal impinging thereon; and second layers forming a capacitance component that is connected in series with the reverse-biased semiconductor junction.
ISHIMURA teaches an optical communication system (Fig. 1, avalanche photodiode can be employed in an optical communication, [0008]), comprising:
a photodetector (Fig. 1, avalanche photo diode (APD), [0018]) comprising:
a stack of layers (Fig. 1, 3/4/8/9/11/12/18, p type layer/light absorption layer/field relaxation layer/multiplication layer/ n type cap layer/ n type contact layer/n type layer), comprising at least:
first layers including two or more semiconductor layers (Fig. 1, 3/4/8/9/11/12, p type layer/light absorption layer/field relaxation layer/multiplication layer/ n type cap layer/n type contact layer) forming a reverse-biased semiconductor junction ([0007]), configured to produce the electrical signal in response to the optical signal impinging thereon ([0016]); and
second layers (Fig. 1, 18, n type layer) forming a capacitance component (Fig. 1, C1) that is connected in series with the reverse-biased semiconductor junction (Figs. 1/2, [0031-0035]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified BRUNO to incorporate the teachings of ISHIMURA such that an optical communication system, comprising a photodetector comprising: a stack of layers, comprising at least: first layers including two or more semiconductor layers forming a reverse-biased semiconductor junction, configured to produce the electrical signal in response to the optical signal impinging thereon; and second layers forming a capacitance component that is connected in series with the reverse-biased semiconductor junction, so that to having a structure capable of reducing a resistance of a current path when a high frequency current flows (ISHIMURA, [0015]).
Regarding Claim 4, BRUNO as modified by ISHIMURA teaches the optical communication system according to claim 1.
BRUNO further teaches the optical communication system (Fig. 9, [Col. 6, Lines 5-15]), wherein at least one of the layers (Fig. 5, 24, n+ doped GaInAsP layer, [Col. 4, Lines 30-40]) in the stack (Fig. 5, 24/26/28, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]) belongs both to the first layers (Fig. 5, 24/261/281, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]) and to the second layers (Fig. 5, 24/261/281, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]).
Regarding Claim 5, BRUNO as modified by ISHIMURA teaches the optical communication system according to claim 1.
BRUNO further teaches the optical communication system (Fig. 9, [Col. 6, Lines 5-15]), the second layers (Fig. 5, 24/261/281, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]) form a forward-biased semiconductor junction (Fig. 6, D1, [Col. 4, Lines 59-65]), and wherein the one or more voltages (Fig. 6, voltage source, SP, [Col. 60-65]) are set to bias both the forward-biased semiconductor junction (Fig. 6, D1, [Col. 4, Lines 59-65]) and the reverse-biased semiconductor junction (Fig. 6, D2, [Col. 4, Lines 59-65]).
Regarding Claim 10, BRUNO teaches a method of manufacturing (Figs. 4/5, [Col. 4, Lines 5-21]) an optical communication system (Fig. 9, [Col. 6, Lines 5-15]), the method comprising:
disposing, on a substrate (Fig. 5, S), a photodetector (PD) (Figs. 3/4, D1/D2, diodes) for converting an optical signal into an electrical signal (Figs. 6/7, [Col. 4, Lines 56-65]), including disposing:
a stack of layers (Fig. 5, 24/26/28, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]), comprising at least:
first layers (Fig. 5, 24/262/282, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]) including two or more semiconductor layers forming a reverse-biased semiconductor junction configured to produce the electrical signal in response to the optical signal impinging thereon (Fig. 4-7, [Col. 4, Lines 56-65]); and
second layers (Fig. 5, 24/261/281, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]) forming a capacitance component that is connected in series with the reverse-biased semiconductor junction (Figs. 5-7, Col. 5, Lines 12-21]); and
a first electrode (Fig. 5, 291, first metallic contact) and a second electrode (Fig. 5, 292, second metallic contact), configured to (i) apply one or more voltages that reverse-bias the reverse-biased semiconductor junction and (ii) output the electrical signal (Figs. 4-7, Col. 4, Lines 9-14; Col. 4, Line 59 - Col. 5, Line 3]); and
disposing, on a substrate (Fig. 5, S), an optical waveguide (Fig. 9, G2, optical guides) for receiving and guiding the optical signal (Figs. 4/5, G2, [Col. 4, Lines 15-24]) to the PD (Figs. 3/4, D1/D2, diodes).
Though BRUNO teaches that a stack of layers including two or more semiconductor layers forming reverse-biased semiconductor junction and further forming a capacitance that is connected with the reverse-biased semiconductor junction, BRUNO does not explicitly show a method of manufacturing an optical communication system, comprising a photodetector comprising: a stack of layers, comprising at least: first layers including two or more semiconductor layers forming a reverse-biased semiconductor junction, configured to produce the electrical signal in response to the optical signal impinging thereon; and second layers forming a capacitance component that is connected in series with the reverse-biased semiconductor junction.
ISHIMURA teaches a method of manufacturing (Fig. 1, avalanche photodiode can be employed in an optical communication, [0008]), comprising:
a photodetector (Fig. 1, avalanche photo diode (APD), [0018]) comprising:
a stack of layers (Fig. 1, 3/4/8/9/11/12/18, p type layer/light absorption layer/field relaxation layer/multiplication layer/ n type cap layer/ n type contact layer/n type layer), comprising at least:
first layers including two or more semiconductor layers (Fig. 1, 3/4/8/9/11/12, p type layer/light absorption layer/field relaxation layer/multiplication layer/ n type cap layer/n type contact layer) forming a reverse-biased semiconductor junction ([0007]), configured to produce the electrical signal in response to the optical signal impinging thereon ([0016]); and
second layers (Fig. 1, 18, n type layer) forming a capacitance component (Fig. 1, C1) that is connected in series with the reverse-biased semiconductor junction (Figs. 1/2, [0031-0035]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified BRUNO to incorporate the teachings of ISHIMURA such that a method of manufacturing an optical communication system, comprising a photodetector comprising: a stack of layers, comprising at least: first layers including two or more semiconductor layers forming a reverse-biased semiconductor junction, configured to produce the electrical signal in response to the optical signal impinging thereon; and second layers forming a capacitance component that is connected in series with the reverse-biased semiconductor junction, so that to having a structure capable of reducing a resistance of a current path when a high frequency current flows (ISHIMURA, [0015]).
Regarding Claim 13 BRUNO as modified by ISHIMURA teaches the method of manufacturing according to claim 10.
BRUNO further teaches the method of manufacturing (Figs. 4/5, [Col. 4, Lines 5-21]), wherein at least one of the layers (Fig. 5, 24, n+ doped GaInAsP layer, [Col. 4, Lines 30-40]) in the stack (Fig. 5, 24/26/28, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]) belongs both to the first layers (Fig. 5, 24/261/281, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]) and to the second layers (Fig. 5, 24/261/281, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]).
Regarding Claim 14, BRUNO teaches the method of manufacturing (Figs. 4/5, [Col. 4, Lines 5-21]) according to claim 10, wherein disposing the second layers (Fig. 5, 24/261/281, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]) comprises forming a forward-biased semiconductor junction (Fig. 6, D1, [Col. 4, Lines 59-65]), the one or more voltages (Fig. 6, voltage source, SP, [Col. 60-65]) biasing both the forward-biased semiconductor junction (Fig. 6, D1, [Col. 4, Lines 59-65]) and the reverse-biased semiconductor junction (Fig. 6, D2, [Col. 4, Lines 59-65]).
Regarding Claim 19, BRUNO as modified by ISHIMURA teaches the method of manufacturing according to claim 10.
BRUNO further teaches the method of manufacturing (Figs. 4/5, [Col. 4, Lines 5-21]), wherein disposing the stack of layers (Fig. 5, 24/26/28, n+ doped GaInAsP layer/GaInAs layer/p+ doped InP/GaInAs layer, [Col. 4, Lines 30-40]) comprises growing the layers epitaxially on one another ([Col. 4, Lines 25-40]).
Claim(s) 2, 7, 11, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over BRUNO, in view of ISHIMURA, as applied to Claim(s) 1, 4-5, 10, 13-14 and further in view of Shinichi Watanuki et al, (hereinafter WATANUKI), US 20180138325 A1.
Regarding Claim 2, BRUNO as modified by ISHIMURA teaches the optical communication system, according to claim 1.
Though BRUNO teaches the optical communication system, wherein first layer comprise III-V semiconductor compounds (made of elements, Ga, In, As. P), BRUNO as modified by ISHIMURA does not explicitly disclose the optical communication system, wherein the first layers comprise at least a silicon layer and a germanium layer.
WATANUKI teaches the optical communication system (optical communication module, [0040]), wherein the first layers comprise at least a silicon layer and a germanium layer (Fig. 2, SL, silicon layer, [0046]; GL, germanium layer, [0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of WATANUKI such that the optical communication system, wherein the first layers comprise at least a silicon layer and a germanium layer, so that germanium has high compatibility with silicon and thus light receiving elements made of germanium can be advantageously formed into a monolithic pattern on a silicon waveguide (WATANUKI, [0042]).
Regarding Claim 7, BRUNO as modified by ISHIMURA teaches the optical communication system, according to claim 1.
BRUNO as modified by ISHIMURA does not explicitly disclose the optical communication system, wherein the second layers comprise at least one dielectric layer and at least one metal layer that form a capacitor.
WATANUKI teaches the optical communication system (optical communication module, [0040]), wherein the second layers (annotated Figure 5) comprise at least one dielectric layer (Fig. 5, IL, interlayer insulating layer) and at least one metal layer (Fig. 5, PLG1, plug include a conductor film, [0047], [0060]) that form a capacitor (annotated Figure 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of WATANUKI such that the optical communication system, wherein the second layers comprise at least one dielectric layer and at least one metal layer that form a capacitor, so that the capacitive coupling between the n-type germanium layer, NR and the plug, PLG1, and the interlayer insulating layer, IL between the NR and the PLG1 in the Ge photodiode, PD1, functions for a high-frequency electric signal generated by photoelectric conversion on high-frequency optical signal (WATANUKI, [0060]).
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Regarding Claim 11, BRUNO as modified by ISHIMURA teaches the method of manufacturing, according to claim 10.
Though BRUNO teaches the method of manufacturing, wherein first layer comprise III-V semiconductor compounds (made of elements, Ga, In, As. P), BRUNO as modified by ISHIMURA does not explicitly disclose the method of manufacturing, wherein disposing the first layers comprises at least a silicon layer and a germanium layer.
WATANUKI teaches the method of manufacturing ([0061-0062]), wherein disposing the first layers comprises at least a silicon layer and a germanium layer (Fig. 2, SL, silicon layer, [0046]; GL, germanium layer, [0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of WATANUKI such that the method of manufacturing, wherein disposing the first layers comprises at least a silicon layer and a germanium layer, so that germanium has high compatibility with silicon and thus light receiving elements made of germanium can be advantageously formed into a monolithic pattern on a silicon waveguide (WATANUKI, [0042]).
Regarding Claim 16, BRUNO as modified by ISHIMURA teaches the method of manufacturing according to claim 10.
BRUNO as modified by ISHIMURA does not explicitly disclose the method of manufacturing, wherein disposing the second layers comprises disposing at least one dielectric layer and at least one metal layer that form a capacitor.
WATANUKI teaches the method of manufacturing ([0061-0062]), wherein disposing the second layers (annotated Figure 5) comprises disposing at least one dielectric layer (Fig. 5, IL, interlayer insulating layer) and at least one metal layer (Fig. 5, PLG1, plug include a conductor film, [0047], [0060]) that form a capacitor (annotated Figure 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of WATANUKI such that the optical communication system, wherein the second layers comprise at least one dielectric layer and at least one metal layer that form a capacitor, so that the capacitive coupling between the n-type germanium layer, NR and the plug, PLG1, and the interlayer insulating layer, IL between the NR and the PLG1 in the Ge photodiode, PD1, functions for a high-frequency electric signal generated by photoelectric conversion on high-frequency optical signal (WATANUKI, [0060]).
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Claim(s) 3, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over BRUNO as modified by ISHIMURA as applied to Claim(s) 1, 4-5, 10, 13-14 and further in view of Matthias Fertig et al, (hereinafter FERTIG), US 20090179225 A1.
Regarding Claim 3, BRUNO as modified by ISHIMURA teaches the optical communication system, according to claim 1.
BRUNO as modified by ISHIMURA does not explicitly disclose the optical communication system, wherein the stack of layers is compatible for fabrication with a Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process.
FERTIG teaches the optical communication system ([0012]), wherein the stack of layers (Fig. 1, 106/104/102/110, third/second/first/fourth layers) is compatible for fabrication with a Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process ([0005], [0008], [0011], [0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of FERTIG such that the optical communication system, wherein the stack of layers is compatible for fabrication with a Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process, so that the CMOS process offers a whole range of PN-junctions which may be used as detectors, using this approach, high performance detectors have been shown to be feasible (FERTIG, [0005], [0008]).
Regarding Claim 12, BRUNO as modified by ISHIMURA teaches the method of manufacturing, according to claim 10.
BRUNO as modified by ISHIMURA does not explicitly disclose the method of manufacturing, wherein disposing the stack of layers is performed in a Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process.
FERTIG teaches the optical communication system ([0032-0033]), wherein disposing the stack of layers (Fig. 1, 106/104/102/110, third/second/first/fourth layers) is performed in a Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process ([0005], [0008], [0011], [0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of FERTIG such that the method of manufacturing, wherein disposing the stack of layers is performed in a Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process, so that the CMOS process offers a whole range of PN-junctions which may be used as detectors, using this approach, high performance detectors have been shown to be feasible (FERTIG, [0005], [0008]).
Claim(s) 6, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over BRUNO, in view of ISHIMURA, as applied to Claim(s) 1, 4-5, 10, 13-14 and further in view of Yu Li et al, (hereinafter LI), US 20220069153 A1.
Regarding Claim 6, BRUNO as modified by ISHIMURA teaches the optical communication system, according to claim 5.
BRUNO as modified by ISHIMURA does not explicitly disclose the optical communication system, further comprising a third electrode, which is connected between the forward-biased semiconductor junction and the reverse-biased semiconductor junction and is configured to apply an additional voltage for applying a further bias to the forward-biased semiconductor junction and to the reverse-biased semiconductor junction.
LI teaches the optical communication system (optical communication device, a CMOS-compatible avalanche photodetector in silicon photonics platform, 1000, Si APD, [0019]), further comprising a third electrode (Fig. 1, 211, [0027]), which is connected between the forward-biased semiconductor junction and the reverse-biased semiconductor junction (Fig. 1, 211, third electrode forms an anode of the Ge/Si APD, 1000 along with first electrode, 111 and the second electrode, 112 can be couple together electrically to form a cathode of the Ge/Si APD, 1000 is operated by applying high-reverse bias voltage between the anode and cathode of the photodiode, [0027]) and is configured to apply an additional voltage for applying a further bias to the forward-biased semiconductor junction and to the reverse-biased semiconductor junction (Fig. 4, electrical filed distribution of the Ge/Si APD versus bias voltage, [0032]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of LI such that the optical communication system, further comprising a third electrode, which is connected between the forward-biased semiconductor junction and the reverse-biased semiconductor junction and is configured to apply an additional voltage for applying a further bias to the forward-biased semiconductor junction and to the reverse-biased semiconductor junction, so that the bias voltage between the anode and cathode of the photodiode that exploits the photoelectric effect with high internal current gain due to the impact ionization (avalanche effect) to convert light into electricity with high responsivity (LI, [0027]).
Regarding Claim 15, BRUNO as modified by ISHIMURA teaches the method of manufacturing according to claim 14.
BRUNO as modified by ISHIMURA does not explicitly disclose the method of manufacturing, further comprising disposing a third electrode connected between the forward-biased semiconductor junction and the reverse-biased semiconductor junction, for applying an additional voltage that applies a further bias to the forward-biased semiconductor junction and to the reverse-biased semiconductor junction.
LI teaches the method of manufacturing (Fig. 2, method of forming the Ge/Si APD of an optical communication device, [0019]), further comprising disposing a third electrode (Fig. 1, 211, [0027]), connected between the forward-biased semiconductor junction and the reverse-biased semiconductor junction (Fig. 1, 211, third electrode forms an anode of the Ge/Si APD, 1000 along with first electrode, 111 and the second electrode, 112 can be couple together electrically to form a cathode of the Ge/Si APD, 1000 is operated by applying high-reverse bias voltage between the anode and cathode of the photodiode, [0027]), for applying an additional voltage that applies a further bias to the forward-biased semiconductor junction and to the reverse-biased semiconductor junction. (Fig. 4, electrical filed distribution of the Ge/Si APD versus bias voltage, [0032]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of LI such that the method of manufacturing, further comprising disposing a third electrode connected between the forward-biased semiconductor junction and the reverse-biased semiconductor junction, for applying an additional voltage that applies a further bias to the forward-biased semiconductor junction and to the reverse-biased semiconductor junction, so that the bias voltage between the anode and cathode of the photodiode that exploits the photoelectric effect with high internal current gain due to the impact ionization (avalanche effect) to convert light into electricity with high responsivity (LI, [0027]).
Claim(s 8-9, and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over BRUNO, in view of ISHIMURA, as applied to Claim(s) 1, 4-5, 10, 13-14 and further in view of Yun-Chung Na et al, (hereinafter NA), US 20170062508 A1.
Regarding Claim 8, BRUNO as modified by ISHIMURA teaches the optical communication system, according to claim 1.
BRUNO as modified by ISHIMURA does not explicitly disclose the optical communication system, wherein the stack of layers comprises: an N-doped silicon layer; a P-doped silicon layer; an intrinsic (I) germanium layer disposed on the P-doped silicon layer; and an additional N-doped silicon layer disposed on the germanium layer.
NA teaches the optical communication system (Fig. 14, 1400, example photodiodes for detecting visible and near-infrared optical signals, [0100]), wherein the stack of layers (annotated Figure 14) comprises:
an N-doped silicon layer (Fig. 14, 1404, n-Si region);
a P-doped silicon layer (Fig. 14, 1406, p-Si region) disposed on or in the N-doped silicon layer (Fig. 14, 1404, n-Si region);
an intrinsic (I) germanium layer (Fig. 14, 1410, i-GeSi region) disposed on the P-doped silicon layer (Fig. 14, 1406, p-Si region); and
an additional N-doped silicon layer (Fig. 14, 1412, n+-GeSi region) disposed on the germanium layer (Fig. 14, 1410, i-GeSi region).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of NA such that the optical communication system, wherein the stack of layers comprises: an N-doped silicon layer; a P-doped silicon layer; an intrinsic (I) germanium layer disposed on the P-doped silicon layer; and an additional N-doped silicon layer disposed on the germanium layer, so that the stack of layers with different type semiconductors such as Ge, and/or Si, and an alloy germanium-silicon material as the optical absorption efficiencies, and may reduce crosstalk between neighboring pixels (NA, [0015]).
It should be noted that substituting (i-Ge, n-Si) for (i-GeSi, n+-GeSi) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
Regarding Claim 9, BRUNO as modified by ISHIMURA teaches the optical communication system, according to claim 1.
BRUNO as modified by ISHIMURA does not explicitly disclose the optical communication system, wherein the stack of layers comprises: a P-doped silicon layer; an N-doped silicon layer disposed on or in the P-doped silicon layer; an intrinsic (I) germanium layer disposed on the N-doped silicon layer; and an additional P-doped silicon layer disposed on the germanium layer.
NA teaches the optical communication system (Fig. 14, 1400, example photodiodes for detecting visible and near-infrared optical signals, [0100]), wherein the stack of layers (annotated Figure 14) comprises:
a P-doped silicon layer (Fig. 14, 1404, n-Si region);
an N-doped silicon layer (Fig. 14, 1406, p-Si region) disposed on or in the P-doped silicon layer (Fig. 14, 1404, n-Si region);
an intrinsic (I) germanium layer (Fig. 14, 1410, i-GeSi region) disposed on the N-doped silicon layer (Fig. 14, 1406, p-Si region); and
an additional P-doped silicon layer (Fig. 14, 1412, n+-GeSi region) disposed on the germanium layer (Fig. 14, 1410, i-GeSi region).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of NA such that the optical communication system, wherein the stack of layers comprises: a P-doped silicon layer; an N-doped silicon layer disposed on or in the P-doped silicon layer; an intrinsic (I) germanium layer disposed on the N-doped silicon layer; and an additional P-doped silicon layer disposed on the germanium layer, so that the stack of layers with different type semiconductors such as Ge, and/or Si, and an alloy germanium-silicon material as the optical absorption efficiencies, and may reduce crosstalk between neighboring pixels (NA, [0015]).
It should be noted that substituting (n-Si, p-Si, i-Ge) for (p-Si, n-Si, i-GeSi, n+-GeSi) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
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Regarding Claim 17, BRUNO as modified by ISHIMURA teaches the method of manufacturing, according to claim 10.
BRUNO as modified by ISHIMURA does not explicitly disclose the method of manufacturing, wherein the stack of layers comprises: disposing an N-doped silicon layer on the substrate; disposing P-doped silicon layer on or in the N-doped silicon layer; disposing an intrinsic (I) germanium layer disposed on the P-doped silicon layer; disposing and an additional N-doped silicon layer on the germanium layer.
NA teaches the method of manufacturing (Fig. 1, 100, photodiode array by CMOS processing techniques, [0030]), wherein the stack of layers (annotated Figure 14) comprises:
an N-doped silicon layer (Fig. 14, 1404, n-Si region);
a P-doped silicon layer (Fig. 14, 1406, p-Si region) disposed on or in the N-doped silicon layer (Fig. 14, 1404, n-Si region);
an intrinsic (I) germanium layer (Fig. 14, 1410, i-GeSi region) disposed on the P-doped silicon layer (Fig. 14, 1406, p-Si region); and
an additional N-doped silicon layer (Fig. 14, 1412, n+-GeSi region) disposed on the germanium layer (Fig. 14, 1410, i-GeSi region).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of NA such that the method of manufacturing, wherein the stack of layers comprises: an N-doped silicon layer; a P-doped silicon layer; an intrinsic (I) germanium layer disposed on the P-doped silicon layer; and an additional N-doped silicon layer disposed on the germanium layer, so that the stack of layers with different type semiconductors such as Ge, and/or Si, and an alloy germanium-silicon material as the optical absorption efficiencies, and may reduce crosstalk between neighboring pixels (NA, [0015]).
It should be noted that substituting (i-Ge, n-Si) for (i-GeSi, n+-GeSi) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
Regarding Claim 18, BRUNO as modified by ISHIMURA teaches the method of manufacturing, according to claim 10.
BRUNO as modified by ISHIMURA does not explicitly disclose the method of manufacturing, wherein the stack of layers comprises: a P-doped silicon layer; an N-doped silicon layer disposed on or in the P-doped silicon layer; an intrinsic (I) germanium layer disposed on the N-doped silicon layer; and an additional P-doped silicon layer disposed on the germanium layer.
NA teaches the method of manufacturing (Fig. 1, 100, photodiode array by CMOS processing techniques, [0030]), wherein the stack of layers (annotated Figure 14) comprises:
a P-doped silicon layer (Fig. 14, 1404, n-Si region);
an N-doped silicon layer (Fig. 14, 1406, p-Si region) disposed on or in the P-doped silicon layer (Fig. 14, 1404, n-Si region);
an intrinsic (I) germanium layer (Fig. 14, 1410, i-GeSi region) disposed on the N-doped silicon layer (Fig. 14, 1406, p-Si region); and
an additional P-doped silicon layer (Fig. 14, 1412, n+-GeSi region) disposed on the germanium layer (Fig. 14, 1410, i-GeSi region).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have BRUNO as modified by ISHIMURA to incorporate the teachings of NA such that the method of manufacturing, wherein the stack of layers comprises: a P-doped silicon layer; an N-doped silicon layer disposed on or in the P-doped silicon layer; an intrinsic (I) germanium layer disposed on the N-doped silicon layer; and an additional P-doped silicon layer disposed on the germanium layer, so that the stack of layers with different type semiconductors such as Ge, and/or Si, and an alloy germanium-silicon material as the optical absorption efficiencies, and may reduce crosstalk between neighboring pixels (NA, [0015]).
It should be noted that substituting (n-Si, p-Si, i-Ge) for (p-Si, n-Si, i-GeSi, n+-GeSi) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20110147874 A1 – Figure 3
STATEMENT OF RELEVANCE – A cross-sectional view of a photodiode portion may include a pair of PIN photodiodes with multiple layers stacked and doped with p- or n-type semiconductors.
US 20190378949 A1 – Figure 1
STATEMENT OF RELEVANCE – A cross-sectional view illustrating a method of fabricating an optical semiconductor device comprises metal films contacting different Ge and/or Si regions, [0067].
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/ALI NARAGHI/ Primary Examiner, Art Unit 2817
