Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-9 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (hereinafter Jeon1) (US 20210034138 A1) in view of Okamoto et al. (hereinafter Okamoto) (US 20100070106 A1).
As to claim 1, Jeon teaches a communication system comprising:
an electronic control unit (ECU) [FIG. 1: multi-core processor 110],
wherein the ECU is a multiple-circuits controller including a first electronic circuit device [FIG. 4: core 1] and a second electronic circuit device [core 2],
the multiple-circuits controller further includes:
a first power switch [FIG. 4: SW1] disposed on a first power path between a power source and the first electronic circuit device [FIG. 4], the first power switch being configured to selectively switch between a first connected state in which the first electronic circuit device is electrically connected to the power source and a first disconnected state in which the first electronic circuit device is electrically disconnected from the power source [0033: “The first power gating switch SW1 may be arranged between the first power rail PR1 and the CORE1 110a and may be selectively turned on in response to a first power gating signal S1G. The first power rail PR1 and the CORE1 110a may be selectively connected with each other through the first power gating switch SW1.”];
a second power switch [FIG. 4: SW 2] disposed on a second power path between the power source and the second electronic circuit device {FIG. 4], the second power switch being configured to selectively switch between a second connected state in which the second electronic circuit device is electrically connected to the power source and a second disconnected state in which the second electronic circuit device is electrically disconnected from the power source [0033: “The second power gating switch SW2 may be arranged between the second power rail PR2 and the CORE2 110b and may be selectively turned on in response to a second power gating signal S2G. The second power rail PR2 and the CORE2 110b may be selectively connected with each other through the second power gating switch SW2”];
a management frame exchange circuit [logic circuit in the control logic 120] configured to exchange a management frame, as the communication frame, that includes first switch information [operating state of the core 1 110a] and second switch information [operating state of the core 2 110b], the first switch information indicating whether to supply electric power to the first electronic circuit device, the second switch information indicating whether to supply electric power to the second electronic circuit device [0047: “The control logic 120 may determine operating states of the CORE1 110a and the CORE2 110b and generate the first and second power gating signals S1G and S2G based on the determined operating states.”], and
a microcomputer having a processor [logic circuit in the control logic 120] configured to:
switch the first power switch between the first connected state and the first disconnected state according to the first switch information in the management frame that is received by the management frame exchange circuit [FIG.2] [0054: “the control logic 120 may generate the first and second power gating signals S1G and S2G to drive the first and second power gating switches SW1 and SW2 as shown in the table 20 of FIG. 2, according to the operating states of the CORE1 110a and the CORE2 110b.”] 0037-0038]; and
switch the second power switch between the second connected state and the second disconnected state according to the second switch information in the management frame that is received by the management frame exchange circuit [FIG.2] [0054: “the control logic 120 may generate the first and second power gating signals S1G and S2G to drive the first and second power gating switches SW1 and SW2 as shown in the table 20 of FIG. 2, according to the operating states of the CORE1 110a and the CORE2 110b.”].
Jeon does not teach the communication system comprising a plurality of the electronic control units that are connected to each other through an in-vehicle network including a communication bus to exchange a communication frame therebetween.
Okamoto teaches a communication system comprising a plurality of the electronic controllers that are connected each other through an in-vehicle network including a communication bus to exchange a communication frame therebetween [FIG. 4B] [0062: “TCP/IP protocol stacks 27d and 37c according to embodiment 3 select a TCP/IP protocol required when the multiple-core processor 20 in the information system ECU 200 communicates with a multiple-core processor 30 in the information system ECU 300 via the in-vehicle communication line 53 such as LAN provided by Ethernet (registered trademark).”].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of deploying multiple multi-core processor in the system as suggested in Okamoto into Jeon to implement higher computing capability. One having ordinary skill in the art would have been motivated to make such modification to improve computing performance of the system.
As to claim 2, Jeon teaches wherein the first electronic circuit device is a first core, the second electronic circuit device is a second core [FIG. 4: core 1 and core2], the multiple-circuits controller further includes a multiple-cores integrated circuit device having the first core and the second core [0046: “The SoC 100 may include the CORE1 110a and the CORE2 110b”].
As to claim 3, Jeon teaches wherein the first electronic circuit device is a first single-core integrated circuit device that includes a single core, and the second electronic circuit device is a second single-core integrated circuit device that includes a single core [FIG. 4: core 1 and core2].
As to claim 4, Jeon teaches wherein the management frame further includes one or more pieces of activation information indicating whether to activate one or more of the plurality of electronic controllers other than the multiple-circuits controller [0047: “The control logic 120 may determine operating states of the CORE1 110a and the CORE2 110b and generate the first and second power gating signals S1G and S2G based on the determined operating states.”].
As to claim 5, Jeon teaches wherein the power supply control unit is configured to output a control signal indicating whether to switch the first power switch to the first connected state and whether to switch the second power switch to the second connected state [0047: “The control logic 120 may determine operating states of the CORE1 110a and the CORE2 110b and generate the first and second power gating signals S1G and S2G based on the determined operating states.”], and the multiple-circuits controller further includes a power switch control unit configured to switch the first power switch and the second power switch according to the control signal [FIG. 2] [0054: “the control logic 120 may generate the first and second power gating signals S1G and S2G to drive the first and second power gating switches SW1 and SW2 as shown in the table 20 of FIG. 2, according to the operating states of the CORE1 110a and the CORE2 110b.”] [00037-0038].
As to claim 6, Jeon teaches an electronic control device [FIG. 1: multi-core processor 110] included in the communication system according to claim 1 that includes: multiple-circuits controller having a first electronic circuit device [FIG. 4: core 1] and a second electronic circuit device [FIG. 4: core 2]; a first power switch [FIG. 4: SW1] disposed on a first power path between a power source and the first electronic circuit device [FIG. 4]; a second power switch [FIG. 4” SW2] disposed on a second power path between the power source and the second electronic circuit device [FIG. 4], wherein
the first power switch is configured to selectively switch between a first connected state in which the first power path is electrically connected to the power source and a first disconnected state in which the first power path is electrically disconnected from the power source [0033: “The first power gating switch SW1 may be arranged between the first power rail PR1 and the CORE1 110a and may be selectively turned on in response to a first power gating signal S1G. The first power rail PR1 and the CORE1 110a may be selectively connected with each other through the first power gating switch SW1.”], and
the second power switch is configured to selectively switch between a second connected state in which the second power path is electrically connected to the power source and a second disconnected state in which the second power path is electrically disconnected from the power source [0033: “The second power gating switch SW2 may be arranged between the second power rail PR2 and the CORE2 110b and may be selectively turned on in response to a second power gating signal S2G. The second power rail PR2 and the CORE2 110b may be selectively connected with each other through the second power gating switch SW2”],
the electronic control device comprising:
a frame generating unit [logic circuit in the control logic 120] configured to generate a management frame, as a communication frame [0047: “The control logic 120 may determine operating states of the CORE1 110a and the CORE2 110b…”], that includes first switch information [operating state of the core 1 110a] indicating whether to supply electric power to the first electronic circuit device and second switch information [operating state of the core 2 110b] indicating whether to supply electric power to the second electronic circuit device upon determining one of predetermined services to be provided based on a detected event [0053: “For example, the control logic 120 may include a scheduler logic configured to schedule tasks of the CORE1 110a and the CORE2 110b and may determine the operating states of the CORE1 110a and the CORE2 110b based on the scheduled tasks of the CORE1 110a and the CORE2 110b.”]; and
a frame transmitting unit [logic circuit in the control logic 120] configured to transmit the management frame [0047: “The control logic 120 may determine operating states of the CORE1 110a and the CORE2 110b and generate the first and second power gating signals S1G and S2G based on the determined operating states.”] [The determined operating states of the cores are transmitted and executed for generating power gating signals.], wherein
the frame generating unit is further configured to generate the management frame according to the determined one of the predetermined services [0053: “For example, the control logic 120 may include a scheduler logic configured to schedule tasks of the CORE1 110a and the CORE2 110b and may determine the operating states of the CORE1 110a and the CORE2 110b based on the scheduled tasks of the CORE1 110a and the CORE2 110b.”].
As to claim 9, Jeon teaches an electronic control device included in the communication system according to claim 1 comprising:
the first electronic circuit device [FIG. 4: core 1];
the second electronic circuit device [FIG. 4: core 2];
the first power switch [FIG. 4: SW1];
the second power switch [FIG. 4: SW2];
the management frame exchange unit [logic circuit in the control logic 120]; and
the microcomputer having the processor [logic circuit in the control logic 120].
Allowable Subject Matter
Claims 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUXING CHEN whose telephone number is (571)270-3486. The examiner can normally be reached M-F 9-5:30PM.
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/XUXING CHEN/Primary Examiner, Art Unit 2176
1 Jeon was cited as a prior art in the last office action mailed on 04/09/2026.
Prosecution Insights