DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Specie I (Figures 2A-2B) in the reply filed on is acknowledged.
Applicant indicates that pending claims 1-15 and 19-23 (with claims 21-23 are newly added) are read on the elected Specie I (Figures 2A-2B). Applicant also canceled claims 16-18.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
For claim 21, the recitation “a second control signal” on line 8 is indefinite because it is unclear antecedent basis with “a second control signal” recited earlier on line 4. To overcome this indefinite problem, the recitation “a second control signal” on line 8 should be changed to “the second control signal”. Clarification and/or appropriated correction is required.
Claims 22-23 are indefinite because they depend on claim 21.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 11-13 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Na et al. (US 2011/0163789).
For claim 1, Figure 2 of Na et al. teaches an integrated circuit, comprising: a master circuit (20), configured to receive an input clock signal (CLK1) and generate an intermediate clock signal (CLK2) based on a first half (any combination of QB[1]…QB[7]) and a second half (the other of the combination of QB[1]…QB[7], i.e., the left over from the first half) of a first trimming code (QB[1]…QB[7]); and a slave circuit (21), electrically connected to the master circuit (20), and configured to receive the intermediate clock signal (CLK2) and generate an output clock signal (CLK3) from the intermediate clock signal (CLK2) based on a first half (any combination of Q[1]…Q[7]) and a second half (the other of the combination of Q[1]…Q[7], i.e., the left over from the first half) of a second trimming code (Q[1]…Q[7]), wherein the first trimming code (QB[1]…QB[7]) is complementary to the second trimming code (Q[1]…Q[7]).
For claim 2, Figure 2 of Na et al. teaches wherein the master circuit (20) comprises: a first trimming circuit (any combination of P18, P19 … P24; one possible example is P18-P19), configured to receive the first half (the corresponding of the combination of QB[1], QB[2] … QB[7], for example QB[1]-QB[2] for P18-P19) of the first trimming code (QB[1]…QB[7]) to provide a first voltage (voltage at junction of P18 and P11, or at junction of P19 and P12); a second trimming circuit (any other combination of N18, N19…N24, one possible example is N20 (not show) … N24]), configured to receive the second half (the corresponding of the combination of QB[1], QB[2] … QB[7], for example: QB[3] (not show) …QB[7] for N20 (not show) … N24) of the first trimming code (QB[1]…QB[7]) to provide a second voltage (the voltage at the junction of N19 (not show) and N13 (not show), … or junction of N14 and N17); and a master compensation circuit (200, P11, P12…P17; N11, N12 … N17), configured to receive the input clock signal (CLK1) and generate the intermediate clock signal (CLK2) from the input clock signal (CLK1) based on the first voltage (voltage at junction of P18 and P11, or junction of P19 and P12) and the second voltage (the voltage at the junction of N19 (not show) and N13 (not show), … or junction of N14 and N17).
For claim 3, Figure 2 of Na et al. teaches the first trimming circuit (any combination of P18, P19 … P24; one possible example is P18-P19) comprises a plurality of P-type transistors, each receiving a respective bit of the first half of the first trimming code (QB[1]-QB[7]); and the second trimming circuit (any other combination of N18, N19…N24, one possible example is N20 (not show) … N24]) comprises a plurality of N-type transistors, each receiving a respective bit of the second half of the first trimming code (QB[1]-QB[7]).
For claim 11, it is seen that Figure 2 of Na et al. teaches wherein the first half and the second half of the first trimming code (QB[1]-QB[7]) refers to an upper half and a lower half of the first trimming code (QB[1]-QB[7]), respectively (for example, it is reasonable to read from Figure 2 for QB[4] (not show) … QB[7] as the first half and QB[1] … QB[3] (not show) as the second half of the first trimming code QB[1]-QB[7]).
For claim 12, it is seen that Figure 2 of Na et al. teaches wherein the first half and the second half of the first trimming code (QB[1]-QB[7]) refers to a lower half and an upper half of the first trimming code (QB[1]-QB[7]), respectively (for example, it is reasonable to read from Figure 2 for QB[1] … QB[3] (not show) as the first half and QB[4] (not show) … QB[7] as the second half of the first trimming code QB[1]-QB[7]).
For claim 13, it is seen that Figure 2 of Na et al. teaches wherein the first half and the second half of the first trimming code (QB[1]-QB[7]) refers to even-number indexed bits and an odd-number indexed bits of the first trimming code (QB[1]-QB[7]), respectively (for example, it is reasonable to read from Figure 2 for QB[2], QB[4] (not show) and QB[6] (not show) as the first half; and QB[1], QB[3] (not show), QB[5] (not show), and QB[7] as the second half of the first trimming code QB[1]-QB[7]).
For claim 19, Figure 2 of Na et al. teaches a method, comprising: providing a master compensation circuit (200, P11, P12…P17; N11, N12 … N17) and a slave compensation circuit (210, P31, P32 … P37, N31, N32 … N37) connected in series; utilizing the master compensation circuit (200, P11, P12…P17; N11, N12 … N17) to generate an intermediate clock signal (CLK2) from an input clock signal (CLK1) through a first trimming circuit (any combination of P18, P19 … P24; one possible example is P18-P19) and a second trimming circuit (any other combination of N18, N19…N24, one possible example is N20 (not show) … N24]) which receive a first half (any combination of QB[1]…QB[7], for example QB[1]-QB[2] for P18-P19) of a first trimming code (QB[1]…QP[7]) and a second half (the other of the combination of Q[1]…Q[7], i.e., the left over from the first half; for example: QB[3] (not show) …QB[7] for N20 (not show) … N24) of the first trimming code (QB[1]…QP[7]), respectively; and utilizing the slave compensation circuit (210, P31, P32 … P37, N31, N32 … N37) to generate an output clock signal (CLK3) from the intermediate clock signal (CLK2) through a third trimming circuit (any combination of P31, P32 … P37; one possible example is P31-P32) and a fourth trimming circuit (any other combination of N31, N32…N37, one possible example is N33 (not show) … N37]) which receive a first half (any combination of Q[1]…Q[7], for example Q[1]-Q[2] for P38-P39) of a second trimming code (Q[1]…Q[7]) and a second half (the other of the combination of Q[1]…Q[7], i.e., the left over from the first half; for example: Q[3] (not show) …Q[7] for N40 (not show) … N44) of the second trimming code (Q[1]…Q[7]), respectively, wherein the second trimming code (Q[1]…Q[7]) is complementary to the first trimming code (QB[1]…QP[7]).
For claim 20, it is seen that Figure 2 of Na et al. teaches wherein the first half and the second half of the first trimming code (QB[1]-QB[7]) comprise a lower half and an upper half of the first trimming code (QB[1]-QB[7]), respectively (for example, it is reasonable to read from Figure 2 for QB[1] … QB[3] (not show) as the first half and QB[4] (not show) … QB[7] as the second half of the first trimming code QB[1]-QB[7]); and the first half and the second half of the second trimming code (Q[1]…Q[7]) comprise an upper half and a lower half of the second trimming code (Q[1]…Q[7]), respectively (for example, it is reasonable to read from Figure 2 for Q[4] (not show) … Q[7] as the first half and Q[1] … Q[3] (not show) as the second half of the second trimming code Q[1]-Q[7]).
Allowable Subject Matter
Claims 4-10 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 21-23 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claim 21 would be allowed because the closet prior art, Na et al. (US 2011/0163789, in Figure 2) teaches an integrated circuit, comprising: a master circuit (20), configured to receive an input clock signal (CLK1) and generate an intermediate clock signal (CLK2) based on a first half and a second half of a first trimming code (QB[1]…QB[7]); and a slave circuit (21), electrically connected to the master circuit, and configured to receive the intermediate clock signal (CLK2) and generate an output clock signal (CLK3) from the intermediate clock signal (CLK2) based on a first half and a second half of a second trimming code (Q[1]…Q[7]), wherein the first trimming code (QB[1]…QB[7]) is complementary to the second trimming code (Q[1]…Q[7]). However, Na et al., either taken alone or in combination, does not teach, as a whole, the limitations “a master circuit, configured to receive an input clock signal and generate an intermediate clock signal based on a first portion and a second portion of a first trimming code, together with a first control signal and a second control signal; and a slave circuit configured to receive the intermediate clock signal, generate a feedback clock signal from the intermediate clock signal based on a first portion and a second portion of a second trimming code, together with the second control signal, and generate an output clock signal based on feedback clock signal, wherein the first trimming code is complementary to the second trimming code, wherein the first control signal is complementary to the second control signal” as recited in the claim.
Claims 22-23 would be allowed because they depend on claim 21.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choi et al. (US 2018/0069532) discloses a duty correction circuit comprising a master compensation circuit (P1-P5, N1-N5), a first trimming circuit (P11-P14), first trimming (CODEB<0>…CODEB<3>), a second trimming circuit (N11-N14), second trimming code (CODE<0>…CODE<3>), a slave compensation circuit (P6-P10, N6-N10), a third trimming circuit (P15-P18), and a fourth trimming circuit (N15-N18).
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch, can be reached at (571) 270-7101. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2836
Prosecution Insights