DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/15/2026 has been entered.
Response to Arguments
Applicant's arguments filed on 05/15/2026 with respect to amended claims 10 - 17 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10 – 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KUROKAWA (US PgPub No. 2017/0063351).
Regarding claim 10, KUROKAWA teaches a semiconductor device comprising: a first transistor (figure 1; Tr5), a second transistor (figure 1; Tr6), a third transistor (figure 1; Tr7), a fourth transistor (figure 1; Tr8), a sensor (figure 1; item LG), a first switch (figure 1; item LAC1), and a memory cell (figure 1 item AM), wherein a first terminal of the sensor is electrically connected to a first wiring (figure 1 item Cout1), wherein a second terminal of the sensor is electrically connected to one of a source and a drain of the first transistor (figure 1 item Cout2), wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor (figure 1 item Tr5 connected to both Tr6 and Tr7), wherein one of a source and a drain of the third transistor is electrically connected to a second wiring (figure 1; item Tr7 connected to Cout2), wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and a first terminal of the first switch (figure 1 item Tr7 connected to items Tr8 and item Tr6 connected to Cout1), wherein the other of the source and the drain of the fourth transistor is electrically connected to a third wiring (figure 1 item Tr8 connected to C2), and wherein the second terminal of the first switch is electrically connected to the memory cell through a fourth wiring (figure 1; item LAC1 connected to AM through Tr5 and/or Tr6).
Regarding claim 11, as mentioned above in the discussion of claim 10, KUROKAWA teach all of the limitations of the parent claim. Additionally, KUROKAWA teaches wherein a gate of the second transistor is electrically connected to a fifth wiring (figure 1 item Tr6 connected to item C1), and wherein a gate of the fourth transistor is electrically connected to a sixth wiring (Tr6 connected to V00).
Regarding claim 12, as mentioned above in the discussion of claim 10, KUROKAWA teach all of the limitations of the parent claim. Additionally, KUROKAWA teaches wherein the sensor comprises a photodiode (figures 21A – 21B and 22A – 22C).
Regarding claim 13, as mentioned above in the discussion of claim 10, KUROKAWA teach all of the limitations of the parent claim. Additionally, KUROKAWA teaches wherein the sensor is positioned over the memory cell (figure 1 items LG and AM from left to right direction).
Regarding claim 14, as mentioned above in the discussion of claim 10, KUROKAWA teach all of the limitations of the parent claim. Additionally, KUROKAWA teaches wherein the sensor is positioned over the first switch, and wherein the first switch is positioned over the memory cell (figure 1 items LG, Tr5, and AM from left to right direction).
Regarding claim 15, KUROKAWA teaches a semiconductor device comprising: a first transistor (figure 1; Tr5), a second transistor (figure 1; Tr6), a third transistor (figure 1; Tr7), a fourth transistor (figure 1; Tr8), a sensor (figure 1; item LG), and a memory cell (figure 1 item AM), wherein a first terminal of the sensor is electrically connected to a first wiring (figure 1 item Cout1), wherein a second terminal of the sensor is electrically connected to one of a source and a drain of the first transistor (figure 1 item Cout2), wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor (figure 1 item Tr5 connected to both Tr6 and Tr7), wherein one of a source and a drain of the third transistor is electrically connected to a second wiring (figure 1; item Tr7 connected to Cout2), wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor (figure 1 item Tr7 connected to items Tr8 and item Tr6 connected to Cout1), and wherein the other of the source and the drain of the fourth transistor is electrically connected to a third wiring (figure 1 item Tr8 connected to C2).
Regarding claim 16, as mentioned above in the discussion of claim 15, KUROKAWA teach all of the limitations of the parent claim. Additionally, KUROKAWA teaches wherein the sensor comprises a photodiode (figures 21A – 21B and 22A – 22C).
Regarding claim 17, as mentioned above in the discussion of claim 15, KUROKAWA teach all of the limitations of the parent claim. Additionally, KUROKAWA teaches wherein the sensor is positioned over the memory cell (figure 1 items LG and AM from left to right direction).
Allowable Subject Matter
Claims 2 - 9 are allowed.
The following is an examiner's statement of reasons for allowance:
Regarding independent claim 2, the prior art of record fails to teach or fairly suggest a sensor, a first switch, a second switch, and a memory cell, wherein a first terminal of the sensor is electrically connected to a first wiring, wherein a second terminal of the sensor is electrically connected to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor, wherein one of a source and a drain of the third transistor is electrically connected to a second wiring, wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and a first terminal of the first switch, wherein the other of the source and the drain of the fourth transistor is electrically connected to a third wiring, wherein a second terminal of the first switch is electrically connected to a first terminal of the second switch, and wherein the second terminal of the first switch is electrically connected to the memory cell through a fourth wiring; in combination with other elements of the claim.
Regarding claims 2 - 9, claims 2 - 9 are allowed as being dependent from allowed independent claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
INOUE (US PgPub No. 20160155480) teaches a camera system with multiple transistors and circuitry.
MATSUZAKI (US PgPub No. 20160035757) teaches a camera system with multiple transistors and circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Usman A Khan whose telephone number is (571)270-1131. The examiner can normally be reached on M - Th 5:30 AM - 2 PM, F 5:30 AM - Noon.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached on (571)272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Usman Khan
/USMAN A KHAN/Primary Examiner, Art Unit 2637
05/20/2026
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