DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the a temperature observation point [claims 1-3, 5, 9-12, and 17-20] must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 2 is objected to because of the following informalities: in line 2 of the claim, change “Wherein” to --wherein-- to correct a typographical error. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 8-10 and 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakayama (WO2022/181377 A1).
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Regarding claim 1, Nakayama discloses [see Figs 1-2 above] a probe testing apparatus (inspection device 1) comprising: a wafer stage (mounting table 21) including a wafer mounting surface [shown but not numbered also see pg. 2 under “DESCRIPTION OF EMBODIMENTS” paragraph 7] on which a semiconductor wafer (wafer W) is mounted; a temperature sensor (temperature sensor 27) including a temperature observation point exposed on the wafer mounting surface (part of 21) and configured to directly measure a temperature of a rear surface of the semiconductor wafer (W) mounted on the wafer mounting surface (part of 21); a temperature adjustment mechanism (temperature adjustment mechanism 28) configured to adjust a temperature of the wafer stage (21) by heating or cooling the wafer stage (21); and a controller (controller 30) configured to control the temperature adjustment mechanism (28) in such a manner that a measured temperature by the temperature sensor (27) becomes a target temperature.
Regarding claim 2, Nakayama discloses wherein the temperature sensor (27) is a contact type temperature sensor configured to measure a temperature of the semiconductor wafer (W) by the temperature observation point coming into contact with the rear surface of the semiconductor wafer (W).
Regarding claim 8, Nakayama discloses wherein the controller (30) further holds temperature control data [via offset table] in a memory (memory device 33), and performs feedforward control on the temperature adjustment mechanism (28) based on the temperature control data [via offset table] in a probe testing period, and wherein the temperature control data is data generated so as to offset, based on a time-series temperature change in a device under test formed on the semiconductor wafer (W) during the probe testing period, the temperature change.
Regarding claim 9, Nakayama discloses [see Figs 1-2 above] a probe testing system (inspection device 1) comprising a probe card (probe card 24) and a probe testing apparatus (inspection section 20), wherein the probe card (24) includes: a plurality of probes (probes 24a) attached so as to come into contact with a terminal of a device under test formed on a semiconductor wafer (wafer W) during a probe testing; and a non-contact type temperature sensor (temperature sensor 26) attached in such a manner that a temperature observation point is arranged at a predetermined distance from a surface of the semiconductor wafer (W) during the probe testing and configured to measure a temperature of the semiconductor wafer (W) in a non-contact manner, and wherein the probe testing apparatus (20) includes: a wafer stage (mounting table 21) including a wafer mounting surface [shown but not numbered also see pg. 2 under “DESCRIPTION OF EMBODIMENTS” paragraph 7] on which a semiconductor wafer (wafer W) is mounted; a temperature adjustment mechanism (temperature adjustment mechanism 28) configured to adjust a temperature of the wafer stage (21) by heating or cooling the wafer stage (21); and a controller (controller 30) configured to acquire a measured temperature by the temperature sensor (26) attached to the probe card (24) and to control the temperature adjustment mechanism (28) based on the measured temperature.
Regarding claim 10, Nakayama discloses wherein the temperature observation point of the temperature sensor (26) is arranged above an inner region of the device under test [see Figs 5A-5C where sensor 26 is placed in the middle of wafer W] and at a position where the plurality of probes (24a) is not arranged, and wherein the controller (30) controls the temperature adjustment mechanism (28) in such a manner that the measured temperature becomes a target temperature.
Regarding claim 16, Nakayama discloses wherein the controller (30) further holds temperature control data [via offset table] in a memory (memory device 33), and performs feedforward control on the temperature adjustment mechanism (28) based on the temperature control data [via offset table] in a probe testing period, and wherein the temperature control data is data generated so as to offset, based on a time-series temperature change in a device under test formed on the semiconductor wafer (W) during the probe testing period, the temperature change.
Regarding claim 17, Nakayama discloses [see Figs 1-2 above] a probe card (probe card 24) to be used in a probe testing of a device under test formed on a semiconductor wafer (wafer W), the probe card (24) comprising: a plurality of probes (probes 24a) attached so as to come into contact with a terminal of the device under test (part of W) during the probe testing; and a non-contact type temperature sensor (temperature sensor 26) attached in such a manner that a temperature observation point is arranged at a predetermined distance from a surface of the semiconductor wafer (W) during the probe testing and configured to measure a temperature of the semiconductor wafer (W) in a non-contact manner.
Regarding claim 18, Nakayama discloses wherein the temperature observation point of the temperature sensor (26) is arranged above an inner region of the device under test [see Figs 5A-5C where sensor 26 is placed in the middle of wafer W] and at a position where the plurality of probes (24a) is not arranged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3, 11-12 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakayama (WO2022/181377 A1).
Regarding claim 3, Nakayama discloses the temperature sensor (27), wherein the temperature observation point of the temperature sensor (27) is arranged within a region of the wafer mounting surface (part of 21). However, the prior art does not disclose a plurality of the temperature sensors as claimed. It would be obvious to have more than one temperature sensor where needed [see MPEP 2144.04 In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)]. It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have more than one temperature sensor since it was held that that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.
Regarding claim 11, Nakayama discloses the temperature sensor (26), wherein the temperature observation point of the temperature sensor (26) is arranged above an outer region of the device under test (part of W) during the probe testing, and wherein the controller (30) predicts a temperature of the device under test (part of W) as a predicted temperature based on the measured temperatures by the temperature sensor (26), and controls the temperature adjustment mechanism (28) in such a manner that the predicted temperature becomes a target temperature. However, the prior art does not disclose a plurality of the temperature sensors as claimed. It would be obvious to have more than one temperature sensor where needed [see MPEP 2144.04 In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)]. It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have more than one temperature sensor since it was held that that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.
Regarding claim 12, Nakayama discloses the temperature sensor (26), wherein the temperature observation point of the temperature sensor (26) is arranged within a region of the probe card (24). However, the prior art does not disclose a plurality of the temperature sensors as claimed. It would be obvious to have more than one temperature sensor where needed [see MPEP 2144.04 In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)]. It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have more than one temperature sensor since it was held that that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.
Regarding claim 19, Nakayama discloses the temperature sensor (26), wherein the temperature observation point of the temperature sensor (26) is arranged above an outer region of the device under test during the probe testing. However, the prior art does not disclose a plurality of the temperature sensors as claimed. It would be obvious to have more than one temperature sensor where needed [see MPEP 2144.04 In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)]. It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have more than one temperature sensor since it was held that that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.
Regarding claim 20, Nakayama discloses the temperature sensor (26), wherein the temperature observation point of the temperature sensor (26) is arranged within a region of the probe card (24). However, the prior art does not disclose a plurality of the temperature sensors as claimed. It would be obvious to have more than one temperature sensor where needed [see MPEP 2144.04 In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)]. It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have more than one temperature sensor since it was held that that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 for details.
Allowable Subject Matter
Claims 4-7 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: regarding claims 4 and 13, the primary reason for the allowance of the claims is due to the temperature adjustment mechanism includes a plurality of adjustment regions dividing the region of the wafer mounting surface, and is configured to adjust temperatures of the plurality of adjustment regions individually. Since claims 5-7 depend from claim 4 and claims 14-15 depend from claim 13, they also have allowable subject matter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERMELE M HOLLINGTON whose telephone number is (571)272-1960. The examiner can normally be reached Mon-Fri 7:00am-3:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee E Rodak can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JERMELE M HOLLINGTON/ Primary Examiner, Art Unit 2858
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