DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1–12 are pending and have been examined on the merits below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit / National Stage Information
This application does not claim the benefit of any prior-filed U.S. application under 35 U.S.C. §§ 119(e), 120, 121, 365(c), or 386(c).
Foreign Priority
Acknowledgment is made of applicant’s claim of foreign priority under 35 U.S.C. § 119(a)–(d) to German Patent Application No. DE 10 2023 210 709.0, filed October 30, 2023. A certified copy of the foreign application is in the file wrapper. The certified copy1 was received by the Office on January 21, 2025.
Information Disclosure Statement
The information disclosure statements filed October 9, 2024 and December 5, 2024 have been considered. Both IDS papers were filed before the first Office action on the merits. See 37 CFR 1.97.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. See 37 CFR 1.72(a) and MPEP § 606.01. The following title or similar is suggested:
Vertical Trench Field-Effect Transistor Having a Shielding Zone Under Fewer Than All Trenches and Body Connections Extending Into the Drift Region
Drawings
Figure 3 is labeled Related Art and is acceptable as such.
Claim Interpretation
The claims are given their broadest reasonable interpretation consistent with the specification as it would be understood by one of ordinary skill in the art. See MPEP § 2111.
The term first conductor type is interpreted as n-type in the disclosed embodiments, and second conductor type as p-type, with the polarities reversible as the specification states.
The phrase a doped zone of the second conductor type in the first connection zone below a first trench of the trenches, and the first connection zone below a second trench of the trenches does not have a doped zone of the second conductor type is interpreted to require a shielding-type region of the second conductor type under at least one trench of the recited plurality and the absence of that region under at least one other trench of the plurality.
Fins is interpreted to cover the semiconductor mesas that remain between adjacent trenches, including mesas narrowed by cyclic oxidation as in Figures 1D–1E.
Device claims 1–6 are product claims. Recited manufacturing history, if any, is treated under MPEP § 2113.
Claim Rejections — 35 U.S.C. § 112
The following is a quotation of 35 U.S.C. 112(b):
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1–12 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Ambiguity. Regarding independent claims 1 and 7, the channel zone is recited as “of the first conductor type, or of a second conductor type complementary to the first conductor type.” The claims then require “body connection regions of the second conductor type, which electrically contact the channel zone.” If the channel zone is of the first conductor type, that contact is a pn junction; if the channel zone is of the second conductor type, the contact is same-type. Only the complementary-type body is disclosed.
Unclear. Regarding claims 1 and 7, “a control electrode arranged in the trenches, the electrode being adjacent to the channel zone” uses a singular electrode arranged in plural trenches. It is unclear whether one continuous electrode occupies every trench or whether each trench contains a control electrode. Claim 2 then recites a respective electrode in each trench distinct from the control electrode.
Dependent claims 2-6 and 8-12 do not alleviate the indefiniteness from the independent claims and are rejected for incorporating the indefiniteness from independent claims 1 and 7, respectively.
Claim Rejections — 35 U.S.C. §§ 102 and 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Prior Art Rejections Based on Primary Reference Lichtenwalner
Lichtenwalner, U.S. Patent No. 11,563,080 B2 (Wolfspeed, Inc.; filed April 30, 2020; published November 4, 2021 as U.S. 2021/0343834 A1; granted January 24, 2023) (“Lichtenwalner”) is prior art under 35 U.S.C. § 102(a)(1).
Figures 1 and 2 of Lichtenwalner are described as examples of previously used shielding approaches. The anticipation rejection below is based on the structure shown and described in Figure 2 of that printed publication, not on Lichtenwalner’s later segmented-trench embodiments. Lichtenwalner does not cite a separate earlier patent as the source of Figure 2. Citation of a source patent is not required. The Figure 2 disclosure itself is a printed publication before the October 30, 2023 effective filing date.
Zundel et al., DE 102 24 201 B4 (Infineon Technologies AG; grant publication November 25, 2010) (cited on the IDS; “Zundel ’201”) is prior art under 35 U.S.C. § 102(a)(1). The present specification identifies Zundel ’201 as the related-art starting point and reproduces its structure as Figure 3.
Aichinger et al., U.S. Patent No. 10,074,741 B2 (Infineon Technologies AG; priority March 3, 2015; granted September 11, 2018) is the U.S. counterpart of DE 10 2015 103 072 A1 (cited on the IDS) and is prior art under 35 U.S.C. § 102(a)(1) (“Aichinger”).
Claims 1, 3–6, 7, and 10–12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lichtenwalner.
Exemplary Figure 2 from Lichtenwalner
PNG
media_image1.png
1035
1640
media_image1.png
Greyscale
Regarding independent claim 1, Lichtenwalner Figure 2 and the accompanying description at col. 7, line 1 through col. 8, line 9 teach:
a vertical field effect transistor structure (trench MOSFET 200; FIG. 2; col. 7, ll. 10–16; MOSFET 200 is a vertical trench device with drain contact 192 on the bottom of substrate 110 and source contacts 190 on the top surface, so current flows vertically through drift region 120), comprising:
a semiconductor body (semiconductor layer structure 106; FIG. 2; col. 7, ll. 10–25; structure 106 is the stack of substrate 110, drift 120, p-wells 170, and source 160 that is the claimed body) having a first connection zone (n-type drift region 120 together with n+ substrate 110 / drain contact 192; FIG. 2; col. 7, ll. 16–20 and 50–54; 120/110 sit on the drain side of the channel) and a second connection zone (n+ source regions 160; FIG. 2; col. 7, ll. 45–50; 160 is n-type on the source side of p-well 170) each being of a first conductor type (n-type; same cites; both 110/120 and 160 are n-type);
a channel zone of a second conductor type complementary to the first conductor type (p-wells 170; FIG. 2; col. 7, ll. 20–25; 170 is p-type, complementary to n-type 160 and 120), arranged between the first and second connection zones (FIG. 2; 170 sits between 160 above it and 120 below it);
a plurality of trenches (180; FIG. 2; col. 7, ll. 26–35; openings 180 are etched from the source side into structure 106, so 180 reads on the claimed trenches) extending into the semiconductor body (106), the trenches (180) reaching from the second connection zone (160) through the channel zone (170) into the first connection zone (120) and forming fins of the channel zone and of the second connection zone (mesas of 170 and 160 left between adjacent trenches 180; FIG. 2; col. 7, ll. 26–35);
a control electrode (gate electrodes 184; FIG. 2; col. 7, ll. 35–45 and col. 8, ll. 1–5; 184 is the insulated gate and, in FIG. 2, occupies every other trench 180) arranged in the trenches (180), the electrode being adjacent to the channel zone (170) and insulated from the semiconductor body (gate insulating layer 182; FIG. 2; col. 7, ll. 35–45; 182 stands between 184 and 170);
a reverse current path connected between the first and second connection zones (120/110 and 160) and in parallel with the channel zone (170), the reverse current path including at least one pn transition and being configured to conduct when a threshold voltage applied between the first and second connection zones is reached (pn junction of p-type shielding patterns 240 / p-wells 170 with n-type drift 120, tied to source contacts 190; FIG. 2; col. 7, ll. 30–40 and col. 7, l. 57 through col. 8, l. 9; when the drain is negative relative to the source the 240/120 junction is forward biased and conducts in parallel with the MOS channel);
wherein the semiconductor body (106) includes a doped zone of the second conductor type (deep buried p-type shielding patterns 240; FIG. 2; col. 7, ll. 30–40 and col. 8, ll. 1–5; 240 is p-type) in the first connection zone (120) below a first trench of the trenches (under the source / intervening trenches 180; 240 sits directly under a first set of trenches 180);
and the first connection zone (120) below a second trench of the trenches (the gate trench 180 that holds 184) does not have a doped zone of the second conductor type (FIG. 2; col. 8, ll. 1–5, “the deep buried p-type semiconductor regions 240 and the gates 184 are provided in alternating trenches 180”; the gate trench has 184/182 at its bottom and no 240 under it, so 120 under that second trench has no second-conductor-type doped zone);
wherein the fins include body connection regions of the second conductor type (p-wells 170 and the p-type path from 170 into 240; FIG. 2; col. 7, ll. 30–40 and 45–54), which electrically contact the channel zone (170) and the second connection zone (source contacts 190 sit on 160 and short 160 to 170 and 240);
wherein the body connection regions of the second conductor type (170/240) extend into a drift zone (240 is formed in drift region 120 and is electrically connected to 170; FIG. 2; col. 7, ll. 30–40 and col. 8, ll. 1–9; the p-type body/shield connection leaves the well and continues down into 120 as 240).
Regarding claim 3, Lichtenwalner teaches the reverse / breakdown path through the same p-type body connection and p-shield (p-wells 170 and shielding patterns 240 electrically connected together and forming a pn junction with n-drift 120; FIG. 2; col. 7, l. 57 through col. 8, l. 9; current that forward-biases that junction travels through the body connection regions of the second conductor type and through the doped zone of the second conductor type).
Regarding claim 4, Lichtenwalner teaches a first connection zone with a lower-doped drift region of the first conductor type and a higher-doped drain region of the first conductor type (lightly-doped n− drift 120 on heavily-doped n+ substrate 110; FIG. 2; col. 7, ll. 16–20), the doped zone of the second conductor type arranged in the drift region (p-type shielding patterns 240 in drift 120; col. 7, ll. 30–35), and the body connection regions extending into the drift region (240 is in 120 and is tied to p-well 170; col. 7, ll. 30–40).
Regarding claim 5, Lichtenwalner teaches that an upper portion of n-type drift region 120 may include an n-type current spreading layer (col. 7, ll. 18–20). That CSL is a first-conductor-type spreading zone between the first connection zone and the channel zone. To the extent a separately claimed dopant-ratio spreading zone is required, see the § 103 rejection based on Aichinger.
Regarding claim 6, Lichtenwalner teaches a wide band-gap semiconductor material including silicon carbide (SiC substrate 110; col. 1, ll. 21–27; col. 7, ll. 16–18; the body of MOSFET 200 is formed in silicon carbide, which is the claimed wide-bandgap semiconductor material).
Regarding independent claim 7, Lichtenwalner teaches the corresponding method. Provide the semiconductor body (form semiconductor layer structure 106 with n+ substrate 110, n− drift 120, p-well 170, and n+ source 160; FIG. 2; col. 7, ll. 10–25). Form a plurality of trenches extending from the second connection zone through the channel zone into the first connection zone, leaving fins (etch trenches 180 through source 160 and well 170 into drift 120; col. 7, ll. 26–35). Form a control electrode in the trenches, insulated from the body and adjacent the channel (form gate insulator 182 and gate 184 in alternating trenches 180; col. 7, ll. 35–45; col. 8, ll. 1–5). Form a reverse current path including a pn transition (implant p-type shielding patterns 240 in drift 120 under the intervening trenches and connect them to source contacts 190; col. 7, ll. 30–40 and col. 7, l. 57 through col. 8, l. 9). Form a doped zone of the second conductor type in the first connection zone below a first trench and omit that doped zone below a second trench (240 and 184 in alternating trenches 180; col. 8, ll. 1–5). Form body connection regions in the fins that contact the channel zone and the second connection zone and that extend into a drift zone (source contact 190 shorts source 160 to p-well 170 and to p-shield 240 in drift 120; col. 7, ll. 30–54).
Regarding claims 10–12, see claims 3–5. The method steps that produce the structure of claims 3–5 are taught by the same Lichtenwalner disclosure.
Claims 2, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenwalner in view of Zundel ’201.
Regarding claim 2, Lichtenwalner teaches the reverse / blocking path and source-connected contacts associated with the shielded trenches (source contacts 190 in the intervening trenches 180 of FIG. 2). Lichtenwalner does not expressly show a source-connected electrode inside the first trench that contacts the p-doped zone at the trench bottom and is insulated from the control electrode.
Zundel ’201 teaches exactly that electrode arrangement: electrode 80 in trench 60, insulated from gate electrode 40 by insulation 70, electrically connected to n+ source 30, and contacting p-doped shielding zone 90 at the trench bottom (present application FIG. 3, identified as Zundel ’201).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to put Zundel ’201’s source-connected trench electrode 80 into Lichtenwalner’s shielded trench of the alternating pair, so that the electrode contacts shielding pattern 240 at the trench bottom and is insulated from gate 184. The rationale is MPEP § 2143(I)(A) (combining prior-art elements according to known methods to yield predictable results) and § 2143(I)(B) (simple substitution of one known shield-contact arrangement for another).
Finding 1. Lichtenwalner already grounds the deep p-shield to source. Zundel ’201 teaches a known, compact way to make that ground: a conductor in the same trench, insulated from the gate, landing on the p-shield at the trench bottom.
Finding 2. One of ordinary skill designing a shielded trench FET knew both the mesa source contact of Lichtenwalner FIG. 2 and the in-trench source electrode of Zundel ’201 as alternative body/shield contacts.
Finding 3. The result was predictable: the shield remains source-tied, the gate remains isolated, and mesa area used for a topside body contact can be reduced, which is the reason Zundel ’201 gives for electrode 80.
Regarding claim 8, forming the p-type shield and the body connection regions in a common implantation step is an obvious process consolidation. Lichtenwalner forms both by implantation into regions exposed by the trenches. Combining two p-type implants into one is MPEP § 2144.06. The present specification itself states that one step or two steps may be used.
Regarding claim 9, see claim 2. The Zundel ’201 in-trench electrode is a method of forming the reverse path inside the trenches with a first electrode contacting the p-doped zone at the bottom of the first trench.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenwalner in view of Aichinger.
Regarding claims 5 and 12, Lichtenwalner already teaches an optional n-type current spreading layer in the upper portion of drift 120 (col. 7, ll. 18–20) and therefore comes close to claims 5 and 12 without Zundel ’201. Zundel ’201 is directed to the in-trench source electrode of claims 2, 8, and 9 and is not needed here. Aichinger teaches current-spread zones in the drift between the diode / p-regions and the body, with a mean dopant concentration at least twice that of the drift zone (US 10,074,741, claim 1; counterpart of DE 10 2015 103 072 A1, cited on the IDS). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form Lichtenwalner’s CSL, between drift 120 and p-well 170, with the higher first-conductor-type doping taught by Aichinger. The rationale is MPEP § 2143(I)(A). Finding 1: Lichtenwalner already places an n-type CSL under the channel. Aichinger supplies a known doping relationship for that layer. Finding 2: one of ordinary skill used a higher-doped spreading layer to lower JFET resistance and spread current around p-shields. Finding 3: the result was predictable current spreading without changing Lichtenwalner’s alternating-trench shield.
B. Prior Art Rejections Based on Primary Reference Zundel ’201
Claims 1–12 are rejected under 35 U.S.C. 103 as being unpatentable over Zundel ’201 in view of Lichtenwalner.
Regarding independent claim 1, Zundel ’201 teaches
a vertical field effect transistor structure (n-conducting vertical trench MOSFET with a shielding structure; present application FIG. 3), comprising:
a semiconductor body (100) having a first connection zone (n+ drain 12 and n− drift 14) and a second connection zone (n+ source 30) each being of a first conductor type;
a channel zone of a second conductor type complementary to the first conductor type (p body zone 20), arranged between the first and second connection zones;
a plurality of trenches (60) extending into the semiconductor body from the second connection zone through the channel zone into the first connection zone and forming mesas / fins of the channel zone and of the second connection zone;
a control electrode (gate electrodes 40) arranged in the trenches, adjacent to the channel zone and insulated from the semiconductor body (gate insulation 50);
a reverse current path connected between the first and second connection zones and in parallel with the channel zone, including at least one pn transition and configured to conduct when a threshold voltage is reached (diode of p-doped zone 90 and drift 14 / drain 12; electrode 80 shorted to source 30);
wherein the semiconductor body includes a doped zone of the second conductor type in the first connection zone below a first trench (p-doped shielding zone 90 under trench 60);
wherein the fins include body connection regions of the second conductor type (p+ body connection regions 22) which electrically contact the channel zone (body 20) and the second connection zone (via electrode 80 shorting body 20 to source 30).
Zundel ’201, as illustrated in the related-art Figure 3 of this application, shows a p-doped zone 90 under each depicted trench and does not expressly teach that the first connection zone below a second trench does not have a doped zone of the second conductor type. Zundel ’201 also does not expressly teach that body connection regions 22 extend into the drift zone.
Lichtenwalner Figure 2 teaches the missing pair of limitations: p-type shielding patterns and gate electrodes in alternating trenches, so that a first trench has a deep p-shield in the drift and a second, adjacent trench does not, and the p-type body / shield connection extends into the drift region 120.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zundel ’201 so that the p-shield 90 is formed under a first trench and omitted under a second, adjacent trench, and so that the p+ body connection is driven into the n− drift. The rationale is MPEP § 2143(I)(A) and § 2143(I)(B).
Finding 1. Zundel ’201 already teaches the claimed trench TMOSFET, source-connected trench electrode, p-shield under the trench bottom forming a parallel pn path, and p+ body ties. Lichtenwalner Figure 2 teaches the known alternative of putting the deep p-shield in only every other trench.
Finding 2. One of ordinary skill knew the Ron / short-circuit-current tradeoff that this specification attributes to Zundel ’201: a p-shield under every trench pinches the JFET and raises Ron; omitting the shield under some trenches opens a lower-resistance path between remaining shields. Lichtenwalner states the same reason for an alternating layout.
Finding 3. The results were predictable: fewer shielding implants reduce process complexity in the unshielded trenches and lower the JFET component of Ron, at the accepted cost of a locally weaker shield.
Regarding claim 2, Zundel ’201 teaches the reverse current path running within the trenches, each trench having electrode 80 electrically connected to source 30 and insulated from gate 40, the electrode contacting p-zone 90 at the bottom of the trench.
Regarding claim 3, the combination teaches body connection regions that electrically contact the remaining p-shield when the p+ body connection is extended into the drift into contact with zone 90 / 240, so that a breakdown path runs through the body connections and the p-doped zone.
Regarding claim 4, Zundel ’201 teaches n− drift 14 and n+ drain 12, with p-zone 90 in the drift. The combination extends the body connections into the drift.
Regarding claim 5, Zundel ’201 as described in this specification permits an n-spreading zone 14a between the drift and the body. Providing that spreading zone would have been obvious to improve current distribution. Aichinger also teaches current spread zones for that purpose.
Regarding claim 6, implementing the Zundel ’201 / Lichtenwalner structure in SiC or GaN would have been obvious. Lichtenwalner is a SiC trench FET; this specification states that TMOSFETs of this class are typically used in SiC or GaN.
Regarding independent claim 7 and claims 8–12, the method tracks the structure. Zundel ’201 teaches provide body, etch trenches, form gate, form p-shield under the trench and source-connected electrode 80. Lichtenwalner Figure 2 teaches forming the p-shield under a first trench and not under a second trench, and forming body connections that extend into the drift. A common implantation step (claim 8) is an obvious consolidation (MPEP § 2144.06). Claims 9–12 follow claims 2–5.
Double Patenting
No nonstatutory double patenting rejection is made at this time. The Examiner reserves the right to revisit double patenting after any claim amendments and upon identification of commonly owned applications with patentably indistinct claims.
Conclusion
A shortened statutory period for reply to this Office action is set to expire THREE MONTHS from the mailing date of this action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
22 September 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
1 Should a translation of the foreign application be required to perfect the claim of priority, applicant is reminded that a translation and a statement that the translation is accurate may be required. See 37 CFR 1.55.
Prosecution Insights