Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the application 18/911,080 filed on 10/09/2024.
Claims 1-20 have been examined and are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tu (US 2008/0310242) and in view of Spangler (US 2022/0179960).
Regarding claim 1, Tu discloses a device comprising:
a system (Tu abstract, par. 0034; A non-volatile memory system 100 having a number of individual memory die 102 and a controller 110. Each memory die is an integrated circuit memory chip or die mounted on a substrate or printed circuit board 104); and
a processor of the system on chip that is configured to perform an override of one or more settings of the system on chip based on one or more settings of a setting record that correspond to a part number of the system on chip (Tu abstract, par. 0034 and 0045; A non-volatile memory system 100 having a number of individual memory die 102 and a controller 110. Each memory die is an integrated circuit memory chip or die mounted on a substrate or printed circuit board 104. Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. A second value can be set into the fuse after packaging the device to cause the chip enable signal to essentially be overridden for that particular memory die. See also par. 0012, 0014, 0035, 0042 and 0048).
Tu teaches, a memory system having a number of individual memory die and a controller. Each memory die is an integrated circuit memory chip or die mounted on a substrate or printed circuit board (Tu par. 0034). However, Tu does not explicitly disclose a system on chip and a security processor of the system on chip.
However, in an analogous art, Spangler teaches a system on chip (Spangler par. 0060; The memory subsystem (e.g., implemented as a SoC), which processes computer-executable instructions to control operations of the computing system ); and
a security processor of the system on chip (Spangler par. 0060; The application processor 102 and the security processor 108 may each be an integrated processor and memory subsystem (e.g., implemented as a SoC), which processes computer-executable instructions to control operations of the computing system 100. See also par. 0027);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Spangler with the method and system of Tu, wherein a security processor of the system on chip to provide users with a means for securely verifying system firmware and recovery firmware to ensure system integrity without relying on a manufacturer's proprietary verification process (Spangler abstract).
Regarding claim 2, Tu and Spangler disclose the device of claim 1,
Tu further discloses wherein the security processor resides in an active interposer die of the system on chip and is configured to override one or more soft fuse settings of one or more microprocessors of the system on chip (Tu par. 0034 and 0045; A non-volatile memory system 100 having a number of individual memory die 102 and a controller 110. Each memory die is an integrated circuit memory chip or die mounted on a substrate or printed circuit board 104. The controller 110 is also an integrated circuit chip or die mounted on its own printed circuit board 124. The two printed circuit boards can be mounted to a third printed circuit board (not illustrated). In other implementations, the controller and memory die may be mounted on the same board. The fuse after packaging the device to cause the chip enable signal to essentially be overridden for that particular memory die).
Regarding claim 3, Tu and Spangler disclose the device of claim 2,
Tu further discloses wherein the security processor corresponds to one of the one or more microprocessors and is configured to perform the override of the one or more soft fuse settings of at least one of: the processor; a first one of the one or more microprocessors that, along with the security processor, resides in the active interposer die; or a second one of the one or more microprocessors that resides in a chiplet stacked on the active interposer die (Tu par. 0034 and 0042; A non-volatile memory system 100 having a number of individual memory die 102 and a controller 110. Each memory die is an integrated circuit memory chip or die mounted on a substrate or printed circuit board 104. The controller 110 is also an integrated circuit chip or die mounted on its own printed circuit board 124. The two printed circuit boards can be mounted to a third printed circuit board (not illustrated). In other implementations, the controller and memory die may be mounted on the same board. The programmable circuits each include one or more fuses or other suitable programmable circuitry to reprogram the chip enable signal and/or unique array address for the corresponding memory die).
Spangler further discloses a security processor of the system on chip (Spangler par. 0060; The application processor 102 and the security processor 108 may each be an integrated processor and memory subsystem (e.g., implemented as a SoC), which processes computer-executable instructions to control operations of the computing system 100. See also par. 0027);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Spangler with the method and system of Tu, wherein a security processor of the system on chip to provide users with a means for securely verifying system firmware and recovery firmware to ensure system integrity without relying on a manufacturer's proprietary verification process (Spangler abstract).
Regarding claim 4, Tu and Spangler disclose the device of claim 1,
Tu further discloses wherein further comprising: an external read only memory storing the setting record (Tu par. 0045; A ROM anti-fuse (often just referred to as a ROM fuse) may be set to its low-resistance state causing an alternate signal to be provided in place of the chip enable signal provided on the device bus.).
Regarding claim 5, Tu and Spangler disclose the device of claim 4,
Tu further discloses further comprising: a printed circuit board; and a socket of the printed circuit board, wherein the system on chip resides in the socket and the external read only memory is attached to the printed circuit board at a location outside of the socket (Tu par. 0034; A non-volatile memory system 100 having a number of individual memory die 102 and a controller 110. Each memory die is an integrated circuit memory chip or die mounted on a substrate or printed circuit board 104. The controller 110 is also an integrated circuit chip or die mounted on its own printed circuit board 124. The two printed circuit boards can be mounted to a third printed circuit board (not illustrated). In other implementations, the controller and memory die may be mounted on the same board).
Regarding claim 6, Tu and Spangler disclose the device of claim 4,
Tu further discloses wherein the security processor is configured to read per part soft fuse settings from the external read only memory only if a setting of the system on chip indicates that the override is indicated for the system on chip (Tu par. 0045; The fuse after packaging the device to cause the chip enable signal to essentially be overridden for that particular memory die. A ROM anti-fuse (often just referred to as a ROM fuse) may be set to its low-resistance state causing an alternate signal to be provided in place of the chip enable signal provided on the device bus. See also par. 0055).
Regarding claim 7, Tu and Spangler disclose the device of claim 6,
Spangler further discloses wherein the security processor is configured to modify the setting upon performing the override to indicate that the override is no longer indicated (Spangler par. 0060 and 0077; The security processor 108 may each be an integrated processor and memory subsystem (e.g., implemented as a SoC), which processes computer-executable instructions to control operations of the computing system 100. The security processor 108 may include a single open-drain pin connected to a write-protection signal. This is connected through a resistor to enable a debugger to override that signal during manufacturing).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Spangler with the method and system of Tu, wherein a security processor of the system on chip to provide users with a means for securely verifying system firmware and recovery firmware to ensure system integrity without relying on a manufacturer's proprietary verification process (Spangler abstract).
Regarding claim 8, Tu and Spangler disclose the device of claim 1,
Spangler further discloses wherein the setting record includes per part soft fuse settings and the security processor is configured to read per part soft fuse settings until it finds one or more soft fuse settings corresponding to a serial number of the system on chip (Spangler par. 0016 and 0060; The Mask ROM may configure the application processor to execute a proprietary verification process before executing the read-only portion of the system firmware. For example, the proprietary verification process may cause the application processor to verify that the read-only portion of the system firmware was signed using a unique, hardware-specific key that is hard-coded within (e.g., burned into fuses of) the application processor. If the Mask ROM can verify the read-only portion of the system firmware using the unique, hardware-specific key, the application processor will execute the read-only system firmware. Reliance on a Mask ROM to verify system firmware may prevent users from installing “unofficial” third-party or user-customized firmware that may not be signed with, and therefore, unverifiable using, the unique, hardware-specific key and the security processor 108 may each be an integrated processor and memory subsystem (e.g., implemented as a SoC)).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Spangler with the method and system of Tu, wherein a security processor of the system on chip to provide users with a means for securely verifying system firmware and recovery firmware to ensure system integrity without relying on a manufacturer's proprietary verification process (Spangler abstract).
Regarding claim 9, Tu and Spangler disclose the device of claim 1,
Spangler further discloses wherein the security processor is configured to override one or more soft fuse settings of one or more microprocessors of the system on chip based on addresses of data read, by the security processor, from the setting record (Tu par. 0045; The fuse after packaging the device to cause the chip enable signal to essentially be overridden for that particular memory die. A ROM anti-fuse (often just referred to as a ROM fuse) may be set to its low-resistance state causing an alternate signal to be provided in place of the chip enable signal provided on the device bus).
Spangler further discloses a security processor of the system on chip (Spangler par. 0060; The application processor 102 and the security processor 108 may each be an integrated processor and memory subsystem (e.g., implemented as a SoC), which processes computer-executable instructions to control operations of the computing system 100. See also par. 0027);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Spangler with the method and system of Tu, wherein a security processor of the system on chip to provide users with a means for securely verifying system firmware and recovery firmware to ensure system integrity without relying on a manufacturer's proprietary verification process (Spangler abstract).
Regarding claim 10, Tu discloses a system, comprising:
a printed circuit board that includes a socket and that has an external read only memory attached thereto at a location outside of the socket, wherein the external read only memory stores per part soft fuse values (Tu par. 0034 and 0042; A non-volatile memory system 100 having a number of individual memory die 102 and a controller 110. Each memory die is an integrated circuit memory chip or die mounted on a substrate or printed circuit board 104. The controller 110 is also an integrated circuit chip or die mounted on its own printed circuit board 124. The two printed circuit boards can be mounted to a third printed circuit board (not illustrated). In other implementations, the controller and memory die may be mounted on the same board. The programmable circuits each include one or more fuses or other suitable programmable circuitry to reprogram the chip enable signal and/or unique array address for the corresponding memory die); and
a system on chip residing in the socket, wherein the system on chip includes an active interposer die and a plurality of microprocessors that includes a processor residing in the active interposer die (Tu par. 0043; Numerous types of programmable circuits can be used in order to store the data necessary for reprogramming the chip enable signal and/or unique address for a particular memory die. In general, some type of fuse circuitry is provided to store logic data used in programming the chip enable signal and/or chip address for the die. Because the fuse circuitry is programmed subsequent to device packaging, it should be writable in its packaged state. Anti-fuses provide a convenient means for storing logic data and are used in one embodiment. Anti-fuses have a first logical state corresponding to high resistance and a second logical state corresponding to low resistance),
wherein the security processor is configured to perform an override of one or more soft fuse settings of the system on chip based on one or more of the per part soft fuse values that correspond to a part number of the system on chip (Tu abstract, par. 0034 and 0045; A non-volatile memory system 100 having a number of individual memory die 102 and a controller 110. Each memory die is an integrated circuit memory chip or die mounted on a substrate or printed circuit board 104. Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. A second value can be set into the fuse after packaging the device to cause the chip enable signal to essentially be overridden for that particular memory die. See also par. 0012, 0014, 0035, 0042 and 0048).
Tu teaches, a memory system having a number of individual memory die and a controller. Each memory die is an integrated circuit memory chip or die mounted on a substrate or printed circuit board (Tu par. 0034). However, Tu does not explicitly disclose a system on chip and a security processor of the system on chip.
However, in an analogous art, Spangler teaches a security processor of the system on chip (Spangler par. 0060; The application processor 102 and the security processor 108 may each be an integrated processor and memory subsystem (e.g., implemented as a SoC), which processes computer-executable instructions to control operations of the computing system 100. See also par. 0027);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Spangler with the method and system of Tu, wherein a security processor of the system on chip to provide users with a means for securely verifying system firmware and recovery firmware to ensure system integrity without relying on a manufacturer's proprietary verification process (Spangler abstract).
Regarding claims 11-14; claims 11-14 are directed to a system associated with the device claimed in claims 8-9 and 6-7 respectively. Claims 11-14 are similar in scope to claims 8-9 and 6-7 respectively, and are therefore rejected under similar rationale respectively.
Regarding claims 15-20; claims 15-20 are directed to a method associated with the device claimed in claims 1-2, 8 and 6-7 respectively. Claims 15-20 are similar in scope to claims 1-2, 8 and 6-7 respectively, and are therefore rejected under similar rationale respectively.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANCHIT K SARKER whose telephone number is (571)270-7907. The examiner can normally be reached M-F 8:30 AM-5:30 PM.
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/SANCHIT K SARKER/Primary Examiner, Art Unit 2495
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