DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/09/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The preliminary amendment, filed 12/18/2024 has been entered. Claim 1 has been canceled. Claims 2-20 have been added. Claims 2-20 are pending in the Application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 2-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,768,780. Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter in the instant application is at least fully disclosed in the reference patent.
Claim 2 of the instant application is anticipated by the patent’s claim 1 in that claim 1 of the patent contain all the limitation of claim 2 of the instant application. Please see table below for the claim comparison.
Further, the limitations of other claims are found with minor variations in the teaching of the patent claims 1-20.
Instant Application (18/911,111)
Patent No. 11,768,780
Claim 2: A system comprising:
a dual in-line memory module (DIMM) comprising a plurality of memory devices;
Claim 1: A method of operation of a memory controller, the method comprising:
a driver circuit coupled to the DIMM, wherein the driver circuit is configured to receive a first write command from a memory controller, the first write command to instruct the DIMM to store data; and
sending, with a first time delay, a write command from the memory controller to a driver coupled between the memory controller and a dual in-line memory module (DIMM), wherein the write command is configured to instruct the DIMM to store data; and
a data buffer coupled to the DIMM, wherein the data buffer is configured to receive a second write command from the memory controller, the second write command to cause the data buffer to send the data to the DIMM, wherein the second write command at least partially overlaps in time with the first write command.
sending, with a second time delay, a data buffer control signal from the memory controller to a data buffer coupled between the memory controller and the DIMM, the data buffer control signal to cause the data buffer to send the data to the DIMM, wherein sending the data buffer control signal to the data buffer at least partially overlaps in time with the sending of the write command to the driver.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 5-6, 9-10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Dodd et al US Patent No. 6,862,653, and in view of Chang et al US 20130326125.
Regarding claim 2, Dodd teaches a system (see figure 3) comprising:
a dual in-line memory module (DIMM) comprising a plurality of memory devices (memory devices 130-145);
a driver circuit coupled to the DIMM (command buffer 122), wherein the driver circuit is configured to receive a first write command from a memory controller, the first write command to instruct the DIMM to store data (see col 3 ln 42-45, the memory controller 110 may wish to write data to the memory devices, wherein the memory controller 110 sends address and command information for a write and the data to be written to the buffer 122); and
a data buffer coupled to the DIMM (data buffer 124), wherein the data buffer is configured to receive a second write command from the memory controller, the second write command to cause the data buffer to send the data to the DIMM (see figure 8, col 7 ln 46-60, instead of having the buffer itself or an external device controlling the direction of data flow through the buffer, the memory controller 110 and/or the memory devices 130-145 set the direction of data flow through the buffer 120. Depending on the implementation, a signal either originates from the memory controller 110, or the memory devices 130-145, to the buffer 120″ indicating the present data flow direction of the buffer 120″).
But Dodd fails to teach the second write command at least partially overlaps in time with the first write command.
However, Chang teaches a write command for a buffer overlapping with a write command for a memory module (see para 0027, the time period in which the host terminal 115 transfers and writes 32 KB data into the buffer 1051 through the data write command could overlap with the time periods of only two merging and writing processes. For instance, when a data is transferred and written into the buffer 1051, the first and second merging and writing processes are performed for writing the LSB data and the CSB data).
Therefore, it would have been obvious to modify the write commands of Dodd and further incorporate overlapping the write commands.
The motivation for doing so is to improve processing time as taught by Chang (see para 0032, The processing time periods are allowed to partially overlap with each other. Therefore, for the overall data access, the overall processing time is reduced and the overall data access efficiency is improved).
Regarding claim 3, Dodd further teaches the data buffer is further configured to receive the data from the memory controller in accordance with the second write command (see col 6 ln 28-33, After the delay period has passed, the embedded logic 195 sends out a signal causing the data buffers 123′, 124′ to drive in the opposite direction. The data buffers 123′, 124′ continue to drive in the direction of the memory devices for the required amount of time it takes to write all the data to be written, or written-data, for that write command).
Regarding claim 5, Dodd further teaches the DIMM comprises a plurality of DRAM devices storing the data at a memory location (see col 2 ln 43-56, memory devices 130-145, such as DRAM devices).
Regarding claim 6, Dodd further teaches the second write command comprises a buffer communication (BCOM) bus signal (see col 7 ln 40-60, Depending on the implementation, a signal either originates from the memory controller 110, or the memory devices 130-145, to the buffer 120" indicating the present data flow direction of the buffer 120").
Regarding claims 9-10 and 12-13, please refer to the rejection of claims 2-3 and 5-6 above since the claimed subject matter is substantially similar. The claims recite the corresponding method performed by the system addressed above.
Claims 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Dodd et al US Patent No. 6,862,653, and in view of Dearth et al US 20150378956.
Regarding claim 16, Dodd teaches a system (see figure 3) comprising:
a dual in-line memory module (DIMM) comprising a plurality of memory devices (memory devices 130-145);
a driver circuit coupled to the DIMM (command buffer 122), wherein the driver circuit is configured to receive, a first write command from a memory controller, the first write command to instruct the DIMM to store data (see col 3 ln 42-45, the memory controller 110 may wish to write data to the memory devices, wherein the memory controller 110 sends address and command information for a write and the data to be written to the buffer 120); and
a data buffer coupled to the DIMM (data buffer 124), wherein the data buffer is configured to receive, with a second time delay (see col 8 ln 20-25, In block P630, assuming that the direction of data blow through the buffer is to be changed, a delay period is waited before the direction of data flow is changed), a second write command from the memory controller, the second write command to cause the data buffer to send the data to the DIMM (see figure 8, col 7 ln 40-60, In other embodiments, instead of having the buffer itself or an external device controlling the direction of data flow through the buffer, the memory controller 110 and/or the memory devices 130-145 set the direction of data flow through the buffer 120. Depending on the implementation, a signal either originates from the memory controller 110, or the memory devices 130-145, to the buffer 120" indicating the present data flow direction of the buffer 120"B), wherein the second time delay of the second write command are configured to allow for operation of the DIMM (see col 6 ln 25-28, implements a delay period for the write command to propagate to the memory devices).
But Dodd fails to teach the write command is sent with a first delay, wherein the first delay of the write command is configured to allow for operation of the DIMM.
However, Dearth teaches sending a write command with a delay, wherein the delay of the write command is configured to allow for operation of the DIMM (see para 0006, A training sequence may include multiple commands such as read commands, write commands, activate commands, or other commands that are used to perform other operations. The memory PHY or the DRAM may require commands in the training sequence to be separated by a specified delay time interval).
Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filling date of the claimed invention to modify the write command of Dodd and incorporate any necessary delay.
The motivation of doing so is to satisfy different timing requirements between commands of the memory module.
Regarding claim 17, Dodd further teaches the data buffer is further configured to receive the data from the memory controller in accordance with the second write command (see col 6 ln 28-33, After the delay period has passed, the embedded logic 195 sends out a signal causing the data buffers 123′, 124′ to drive in the opposite direction. The data buffers 123′, 124′ continue to drive in the direction of the memory devices for the required amount of time it takes to write all the data to be written, or written-data, for that write command).
Regarding claim 19, Dodd further teaches the DIMM comprises a plurality of DRAM devices storing the data at a memory location (see col 2 ln 43-56, memory devices 130-145, such as DRAM devices).
Regarding claim 20, Dodd further teaches the second write command comprises a buffer communication (BCOM) bus signal (see col 7 ln 40-60, Depending on the implementation, a signal either originates from the memory controller 110, or the memory devices 130-145, to the buffer 120" indicating the present data flow direction of the buffer 120").
Claims 4, 7, 11, 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of prior arts as applied to claims above, and further in view of Loughner et al US 20100003837.
Regarding claim 4, the combination of Dodd and Chang teaches all the limitation with respect to claim 2 as outlined above.
But the combination of Dodd and Chang fails to teach the driver circuit comprises a register clock driver.
However, Loughner teaches a register clock driver for use with memory device and buffer (see figure 9, registering clock driver 906, para 0054, The eight rank configuration depicted in FIG. 9 includes memory module 902 with a memory buffer device 904 having two full memory ports “A” and “B” and including four registering clock driver devices 906).
Therefore, it would have been obvious to modify the memory system of Dodd and further incorporate register clock driver.
Doing so would allow increasing memory module density and/or performance as taught by Loughner (see para 0055).
Regarding claim 7, the combination of Dodd and Chang teaches all the limitations with respect to claim 2 as outlined above.
But, the combination of Dodd and Dearth fails to teach the driver is configured to send a signal to the DIMM, wherein the signal comprises one of a clock enable (CKE) signals, on-die termination (ODT) signals, chip select (CSN) signals, and chip ID (C2).
However, Loughner teaches driver is configured to send a signal to the DIMM, wherein the signal comprises one of a clock enable (CKE) signals, on-die termination (ODT) signals, chip select (CSN) signals, and chip ID (C2) (see figure 3, command signals 304 including CKE, ODT, CSN, CASN…).
Therefore, it would have been obvious to modify the memory system of Dodd and further incorporate sending different signals to the memory device through the driver.
Doing so would provide necessary signals to the memory device thus allow optimal operation of the system.
Regarding claims 11, 14 and 18, please refer to the rejection of claims 4 and 7 above since the claimed subject matter is substantially similar.
Allowable Subject Matter
Claims 8 and 15 are regarded as comprising allowable subject matter, and would be allowable if (1) rewritten in independent form including all of the limitations of the base claim and any intervening claims and (2) filing and acceptance of the Terminal Disclaimer to overcome the set forth double patenting rejection above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ohta et al US 20010011323 discloses a read/write processing device to improve efficiency of overlapping write commands
Hirobe US 20120287729 discloses a memory device having address/control bus for a buffer and a data bus.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHONG H DANG whose telephone number is (571)272-0470. The examiner can normally be reached Monday-Friday 9:30AM - 6:00PM.
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/PHONG H DANG/Primary Examiner, Art Unit 2184