Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/10/2024 is in
compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure
statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7-14, 17, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al. (US Pat. Pub. 20160266975; hereinafter referred to as Hu) in view of Chang et al. (US Pat. Pub. 20170262337; hereinafter referred to as Chang).
As per claim 1:
Hu teaches a memory (Hu par. 0129, memory module 2000) comprising:
a plurality of data terminals (Hu par. 0130, plurality of data interfaces 2036);
a plurality of data receiving circuits configured to receive data and a parity through the plurality of data terminals (Hu par. 0130-0137, registers 2149 receive data and error information through data interfaces and error interfaces);
an error correction code (ECC) decoder circuit configured to detect errors in the data and the parity based on the data and the parity (Hu par. 0118, ECC engine 1908 configured to correct errors by receiving encoded data and decoding the encoded data. Please note single error correct-double error detect is used as stated in Hu par. 0115); and
an error storage circuit (Hu par. 0122, memory configured to store error information).
Hu does not explicitly disclose store a history of the errors detected by the ECC decoder circuit. However, Chang discloses store a history of the errors detected by the ECC decoder circuit (Chang par. 0018-0020, identify the failing bit location information, DQ, according to the error detection and correction circuitry for storage in the error log storage).
Hu and Chang are analogous arts because they are in the same field of endeavor of memory devices. It would have been obvious to one of ordinary skill in the art to combine Chang’s circuitry to store failing bit location information with the memory of Hu. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it provides a system that is straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective (Chang par. 0026).
As per claim 2:
Hu and Chang further teach the memory of claim 1, wherein the error storage circuit is configured to store the history of error occurrence for each data terminal (Chang par. 0018-0020).
As per claim 3:
Hu and Chang further teach the memory of claim 2, wherein the error storage circuit is configured to count and store a number of error occurrence for each data terminal (Chang par. 0018-0020. Please note it would have been obvious to a person skilled in the art to count a number of error occurrences in addition to storing as it is a straightforward implementation detail that follows storing error history per data terminal).
As per claim 4:
Hu and Chang further teach the memory of claim 2, wherein the plurality of data receiving circuits are configured to operate in synchronization with a data clock (Hu par. 0126-0127, receive a data strobe signal in synchronization with error information and data).
As per claim 5:
Hu and Chang further teach the memory of claim 4, further comprising: a first data clock terminal; a second data clock terminal (Hu par. 0129-0130, plurality of data interfaces. Please note the data interfaces include clock lines as stated in par. 0100); and a data clock receiver configured to receive the data clock through the first and second data clock terminals and transmit the data clock to the plurality of data receiving circuits (Hu par. 0126-0130, receive data strobe signal through the clock lines stated in par. 0100).
As per claim 7:
Hu and Chang further teach the memory of claim 2, wherein the history of error occurrence stored in the error storage circuit is transmitted to a memory controller according to a request of the memory controller (Chang par. 0021, memory controller requests the failing bit location information for extraction).
As per claim 8:
Hu and Chang further teach the memory of claim 5, further comprising: a memory core configured to store data processed by the ECC decoder circuit (Hu par. 0116-0118, memory cell array configured to store data processed by the ECC engine); an ECC encoder circuit configured to generate the parity based on the data read from the memory core (Hu par. 0117, ECC engine configured to calculate ECC bit values according to write data); and a plurality of data transmitting circuits configured to transmit, through the plurality of data terminals, the data read from the memory core and the parity generated by the ECC encoder circuit (Hu par. 0119, plurality of memory devices output the output data through their individual data interfaces as stated in Hu par. 0100).
As per claim 9:
Hu and Chang further teach the memory of claim 8, wherein the plurality of data transmitting circuits are configured to operate in synchronization with a read data strobe signal (Hu par. 0126-0127, data output from the memory cell array is output in synchronization with a data strobe signal).
As per claim 10:
Hu and Chang further teach the memory of claim 9, further comprising: a strobe generation circuit configured to generate the read data strobe signal based on the data clock (Hu par. 0126, DQS modifier outputs a modified data strobe signal); a first read data strobe signal terminal; a second read data strobe signal terminal (Hu par. 0129-0130, plurality of data interfaces, wherein the data interfaces includes strobe lines as stated in Hu par. 0100); and a read data strobe signal transmitter configured to transmit the read data strobe signal through the first and second read data strobe signal terminals (Hu par. 0127, modified output data strobe signal is output through the strobe lines stated in Hu par. 0100).
As per claim 11:
Hu and Chang further teach the memory of claim 7, wherein the error storage circuit is configured to receive a syndrome generated by the ECC decoder circuit (Hu par. 0117, memory cell array receives ECC bits from ECC engine).
As per claim 12:
Hu teaches a memory system (Hu par. 0129, memory module 2000) comprising:
a plurality of data lines (Hu par. 0129-0130, plurality of data interfaces 2036. Please note the data interfaces 2036 includes data lines as stated in par. 0100);
a first data clock line and a second data clock line (Hu par. 0100, the data interfaces 2036 includes strobe lines);
a memory controller configured to transmit data and a parity through the plurality of data lines (Hu par. 0112, controller 1814 transmits data through data interfaces) and transmit a data clock through the first and second data clock lines (Hu par. 0069, transmit a data strobe signal over the data strobe lines); and
a memory configured to receive the data clock through the first and second data clock lines and receive the data and the parity transmitted through the plurality of data lines, in synchronization with the data clock (Hu par. 0126-0127, memory device receives a data strobe signal in synchronization with error information and data),
wherein the memory includes:
an ECC decoder circuit configured to detect errors in the data and the parity based on the data and the parity (Hu par. 0118, ECC engine 1908 configured to correct error by receiving encoded data and decoding the encoded data. Please note single error correct-double error detect is used as stated in par. 0115); and
an error storage circuit (Hu par. 0122, memory configured to store error information).
Hu does not explicitly disclose configured to store a history of the errors detected by the ECC decoder circuit for each data line. However, Chang discloses configured to store a history of the errors detected by the ECC decoder circuit for each data line (Chang par. 0018-0020, identify the failing bit location information, DQ, according to the error detection and correction circuitry for storage in the error log storage. Please note it is interpreted DQ refers to the failing bit location per data line).
Hu and Chang are analogous arts because they are in the same field of endeavor of memory devices. It would have been obvious to one of ordinary skill in the art to combine Chang’s circuitry to store failing bit location information with the memory of Hu. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it provides a system that is straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective (Chang par. 0026).
As per claim 13:
Hu and Chang further teach the memory system of claim 12, wherein the error storage circuit is configured to count and store a number of error occurrences for each data line (Chang par. 0018-0020. Please note it would have been obvious to a person skilled in the art to count a number of error occurrences in addition to storing as it is a straightforward implementation detail that follows storing error history per data terminal).
As per claim 14:
Hu and Chang further teach the memory system of claim 12, wherein the memory further includes a plurality of data receiving circuits configured to receive the data and the parity through the plurality of data lines, in synchronization with the data clock (Hu par. 0130-0137, registers 2149 receive data and error information through data interfaces and error interfaces. Please note the data and error information is received in synchronization with a data strobe signal as stated in Hu par. 0126-0127).
As per claims 17 and 21:
Hu teaches an operating method of a memory system including a memory and a memory controller and a memory system (Hu par. 0133, memory module 2100 including memory device 2101 and controller 2141) comprising:
a plurality of data lines (Hu par. 0129-0130, plurality of data interfaces 2036. Please note the data interfaces 2036 includes data lines as stated in par. 0100);
one or more data clock lines (Hu par. 0100, the data interfaces 2036 includes strobe lines);
a memory controller configured to transmit data and a parity to the plurality of data lines (Hu par. 0112, controller 1814 transmits data through data interfaces) and transmit a data clock to the one or more data clock lines (Hu par. 0069, transmit a data strobe signal over the data strobe lines); and
a memory configured to, in synchronization with the data clock transmitted through the one or more data clock lines, receive the data and the parity through the plurality of data lines (Hu par. 0126-0127, memory device receives a data strobe signal in synchronization with error information and data)
Hu does not explicitly disclose store a history of errors detected by decoding the received data and parity for each data line. However, Chang discloses store a history of errors detected by decoding the received data and parity for each data line (Chang par. 0018-0020, identify the failing bit location information, DQ, according to the error detection and correction circuitry for storage in the error log storage. Please note it is interpreted DQ refers to the failing bit location per data line).
Hu and Chang are analogous arts because they are in the same field of endeavor of memory devices. It would have been obvious to one of ordinary skill in the art to combine Chang’s circuitry to store failing bit location information with the memory of Hu. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it provides a system that is straightforward, cost-effective, uncomplicated, highly versatile, accurate, sensitive, and effective (Chang par. 0026).
As per claim 22:
Hu and Chang further teach the memory system of claim 21, wherein the memory is configured to transmit the history of errors to the memory controller according to a request of the memory controller (Chang par. 0021, memory controller requests the failing bit location information for extraction).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hu-Chang in further view of Qian et al. (US Pat. Pub. 20220021603; hereinafter referred to as Qian).
As per claim 6:
Hu and Chang further teach the memory of claim 4, wherein each of the plurality of data receiving circuits includes: a data receiver (Hu Par. 0100, each data interface include buffers).
Hu and Chang do not explicitly disclose a serial-to-parallel conversion circuit configured to convert a reception result of the data receiver in a serial-to-parallel manner, in synchronization with the data clock. However, Qian discloses a serial-to-parallel conversion circuit configured to convert a reception result of the data receiver in a serial-to-parallel manner, in synchronization with the data clock (Qian par. 0030, serial-to-parallel circuit groups digital data stream bits into parallel blocks in synchronization with a clock signal).
It would have been obvious to one of ordinary skill in the art to combine Qian’s serial-to-parallel circuit with the memory of Hu-Chang because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it provides faster processing and storage.
As per claim 15:
Hu and Chang further teach the memory system of claim 14, wherein each of the plurality of data receiving circuits includes: a data receiver (Hu Par. 0100, each data interface include buffers).
Hu and Chang do not explicitly disclose a serial-to-parallel conversion circuit configured to convert a reception result of the data receiver in a serial-to-parallel manner, in synchronization with the data clock. However, Qian discloses a serial-to-parallel conversion circuit configured to convert a reception result of the data receiver in a serial-to-parallel manner, in synchronization with the data clock (Qian par. 0030, serial-to-parallel circuit groups digital data stream bits into parallel blocks in synchronization with a clock signal).
It would have been obvious to one of ordinary skill in the art to combine Qian’s serial-to-parallel circuit with the memory of Hu-Chang because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it provides faster processing and storage.
Claims 16, 18, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Hu-Chang in further view of Kochavi et al. (US Pat. 11909850; hereinafter referred to as Kochavi).
As per claim 16:
Hu and Chang further teach the memory system of claim 12, wherein the history of the errors stored in the error storage circuit is transmitted from the memory to the memory controller (Chang par. 0021, memory controller requests the failing bit location information for extraction).
Hu and Chang do not explicitly disclose wherein the memory controller is configured to adjust timing of the data and data clock to be transmitted, based on the history of the errors transmitted from the memory. However, Kochavi discloses wherein the memory controller is configured to adjust timing of the data and data clock to be transmitted, based on the history of the errors transmitted from the memory (Kochavi col. 8 lines 40-45, adjust timing of the transmitter and receiver interfaces and the clock. Please note it would have been routine and obvious to use the history of errors to make changes to the memory system).
It would have been obvious to one of ordinary skill in the art to combine Kochavi’s adjusting interface and clock timing with the memory system of Hu-Chang. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it improves the bit error rate (Kochavi col. 8 lines 40-45).
As per claim 18:
Hu and Chang further teach the operating method of claim 17, further comprising: transmitting, by the memory, the history of error occurrences to the memory controller (Chang par. 0021, memory controller requests the failing bit location information for extraction).
Hu and Chang do not explicitly disclose adjusting, by the memory controller, timing of the data clock and the data based on the history of error occurrences. However, Kochavi discloses adjusting, by the memory controller, timing of the data clock and the data based on the history of error occurrences (Kochavi col. 8 lines 40-45, adjust timing of the transmitter and receiver interfaces and the clock. Please note it would have been routine and obvious to use the history of errors to make changes to the memory system).
It would have been obvious to one of ordinary skill in the art to combine Kochavi’s adjusting interface and clock timing with the memory system of Hu-Chang. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it improves the bit error rate (Kochavi col. 8 lines 40-45).
As per claim 23:
Hu and Chang teach the memory system of claim 22.
Hu and Chang do not explicitly disclose wherein the memory controller is configured to adjust timing of the data clock and the data to be transmitted, based on the history of errors transmitted from the memory. However, Kochavi discloses wherein the memory controller is configured to adjust timing of the data clock and the data to be transmitted, based on the history of errors transmitted from the memory (Kochavi col. 8 lines 40-45, adjust timing of the transmitter and receiver interfaces and the clock. Please note it would have been routine and obvious to use the history of errors to make changes to the memory system).
It would have been obvious to one of ordinary skill in the art to combine Kochavi’s adjusting interface and clock timing with the memory system of Hu-Chang. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it improves the bit error rate (Kochavi col. 8 lines 40-45).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hu-Chang-Kochavi in further view of Chien et al. (US Pat. Pub. 20150178001; hereinafter referred to as Chien).
As per claim 19:
Hu, Chang, and Kochavi further teach the operating method of claim 18 and transmitting the history of error occurrences and adjusting the timing of the data clock and the data.
Hu, Chang, and Kochavi do not explicitly disclose performed during a period in which no data transmission or reception is present between the memory and the memory controller. However, Chien discloses performed during a period in which no data transmission or reception is present between the memory and the memory controller (Chien par. 0016, maintenance procedures are performed when the controller is idle).
It would have been obvious to one of ordinary skill in the art to combine Chien’s performing maintenance during an idle period with the operating method of Hu-Chang-Kochavi because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it would prevent any corruption to occur during the maintenance period.
As per claim 20:
Hu, Chang, Kochavi, and Chien further teach the operating method of claim 19, wherein the period includes an all bank refresh operation period of the memory (Chien par. 0016).
It would have been obvious to one of ordinary skill in the art to realize using an all bank refresh operation period, which is an example of a period of memory unavailability in dynamic random access memory, and is merely a design choice.
Conclusion
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/JEFFREY ANDREW YANG/
Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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