DETAILED ACTION
Claims 1-19 are pending and have been examined on the merits below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Benefit
This application is a continuation of International Application No. PCT/CN2022/088028, filed April 20, 2022. Acknowledgment is made of applicant's claim for benefit under 35 U.S.C. 120 and 365(c). The claims are examined with an effective filing date of April 20, 2022. See MPEP 1895.
Foreign Priority
No claim for foreign priority under 35 U.S.C. 119(a)-(d) has been made in this application. The Application Data Sheet claims benefit of International Application No. PCT/CN2022/088028 filed April 20, 2022 as a continuation under 35 U.S.C. 120 and 365(c). That PCT filing is not treated as a 119 priority claim1.
Information Disclosure Statement
The information disclosure statement filed May 13, 2025 has been considered. The submission complies with 37 CFR 1.97. The statement was filed before the first Office action on the merits.
Corresponding Applications / Global Dossier
The Global Dossier identifies a four-member family: this application (US 18/911,277); International Application PCT/CN2022/088028; CN 202280083744; and EP 22 937 835.1 (EP 22937835 / publication family EP 4 485 515).
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 37 CFR 1.72(a); MPEP 606.01.
The following title is suggested: "INTEGRATED-CIRCUIT CHIP HAVING A CONDUCTIVE PILLAR WITH A PARTIAL SIDEWALL METAL-COMPOUND LAYER IN CONTACT WITH A DIELECTRIC, METHOD OF MAKING THE SAME, AND ELECTRONIC DEVICE."
Claim Interpretation
The claims are given their broadest reasonable interpretation consistent with the specification. MPEP 2111.
Product-by-process limitations in the device claims are treated under MPEP 2113. Claim 2 ("formed by using a selective deposition process") and claim 4 ("obtained by performing oxidation treatment and/or nitride treatment on the side surface of the metal pillar") do not distinguish the finished chip from a structurally identical pillar made another way. The burden is on Applicant to show a structural difference in the finished product.
"Metal compound layer" is construed, in view of the specification at least at paragraphs [0012]-[0022] and [0236]-[0245], as a metal oxide, metal nitride, and/or metal oxynitride layer on a side surface of the metal pillar.
Claim 1 requires three things together: (1) a metal compound layer between the metal pillar and the dielectric covering a part of a side surface of the metal pillar; (2) that compound layer in contact with the dielectric; and (3) a side surface of the metal pillar that is not covered by the compound layer also in contact with the dielectric. A continuous, full-sidewall deposited barrier that leaves no bare metal-to-dielectric contact does not meet claim 1 under this reading.
Claim Rejections - 35 USC 112
The following is a quotation of 35 U.S.C. 112(b):
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 11 and 15-19 are rejected under 35 U.S.C. 112(b) as being indefinite.
Regarding claim 11, "oxygen content, nitrogen content, or widths of a plurality of metal compound layers comprised in the plurality of first conductive pillars are not identical" is ambiguous. It is not clear whether the comparison is (a) between neighboring pillars, (b) along the height of one pillar, or (c) both, or how large a difference is required to be "not identical."
Regarding independent claim 15, "a first conductive pattern located on a first intermediate dielectric layer side" lacks a clear antecedent for "first intermediate dielectric layer." Claim 15 already recites "a dielectric layer" in which the hole is formed. It is unclear whether "first intermediate dielectric layer" is that same dielectric layer or a different layer. For examination, the phrase is treated as intending the first conductive pattern to be located on a side of the dielectric layer already recited in claim 15. Applicant should amend to that language. In addition, "a side surface of the metal pillar body originally not in contact with the dielectric layer expands to be in contact with the dielectric layer" is unclear as to whether every residual gap must close or whether a remaining unfilled pocket after the chemical-processing step still meets the claim.
Claims 16-19 are rejected as depending from claim 15.
Allowable Subject Matter
Claims 1-10 and 12-14 are allowed. Claims 11 and 15-19 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action.
The closest art of record is Li et al., WO 2021/184166 A1 ("Li") (published September 23, 2021) taken with Tien et al., U.S. Patent Application Publication No. 2019/0164781 A1 ("Tien"), and the Wu gap-fill paper cited on the IDS. Those references were considered both alone and in combination. No rejection under 35 U.S.C. 102 or 103 is made. The reasons follow.
What Li teaches: Li is a package-level chip structure. Electrical connector 30 includes copper pillar 31 and tin bump 32. One end of pillar 31 is electrically connected to first chip 10; bump 32 is electrically connected to adapter board 20 (Li page 3; FIGS. 5c-5d). Insulating layer 50 "is a copper oxide layer" and "is wrapped on at least part of the side wall of the electrical connector" (Li pages 2-3; FIG. 5c).
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Exemplary FIG. 5c from Li (copper pillar 31, tin bump 32, copper-oxide insulating layer 50 on the sidewall)
What Li does not teach: Pillar 31 is not disposed in a dielectric layer and does not run through a dielectric in the thickness direction. Layer 50 is an outer jacket that separates the pillar from a high-thermal-conductivity medium so the connector is electrically isolated from that medium (Li pages 2-3; FIG. 5c). Li does not show (i) a residual gap inside a via hole that is closed by converting the pillar metal, or (ii) an uncovered metal side surface of the same pillar in contact with the same dielectric that the compound also contacts. Those two contacts with one dielectric hole wall are the third requirement of claim 1.
What Tien teaches: Conductive vias 113, 114 are disposed in dielectric layer 110 and run through that dielectric, coupling lower structure to metal lines 131, 132 (Tien paragraphs [0013]-[0015]; FIG. 1). Intermediate metal layers 141, 142 of Ta, TaN or TiN, 5 A to 200 A thick, sit on the metal lines under metal pillars 151, 152 (Tien paragraphs [0016], [0018]; FIG. 1). Tien's stated problem is voids in high-aspect-ratio BEOL fill; the solution is to deposit three metal layers and etch them so that no voids are generated (Tien paragraphs [0009]-[0010]).
What Tien does not teach: Layers 141, 142 are deposited intermediate films between a metal line and a metal pillar in a horizontal stack. They are not a conversion product of via metal on the sidewall of dielectric 110, and they are not a partial skin that leaves bare via metal in contact with dielectric 110. Tien's process is directed at eliminating voids, not at leaving a residual gap and then oxidizing the exposed metal into that gap.
Why Li and Tien are not combined. A 103 rejection over Li in view of Tien (or the reverse) was considered and is not made, for the following reasons.
First, the references solve opposite problems with opposite sidewall treatments. Li oxidizes the outer sidewall so that surrounding material does not electrically contact the copper. Tien fills a dielectric hole so that the via is a conductor through that dielectric, and uses a deposited Ta/TaN/TiN film as an intermediate layer between two metals, not as an insulator against the dielectric. Wrapping Li's copper-oxide jacket onto Tien's via sidewall would electrically isolate the via from the dielectric. That is Li's goal in a package thermal medium. It is the opposite of claim 1, which requires the uncovered metal of the same pillar to remain in contact with that dielectric.
Second, Tien's intermediate layer is the wrong structure in the wrong place. Paragraphs [0016] and [0018] put Ta/TaN/TiN between metal line 131 and metal pillar 151. That interface is not the via/dielectric sidewall. Using Tien's thickness numbers or nitride materials as if they were a conversion skin on the hole wall is a change of what Tien actually built.
Third, the only reason to oxidize Tien's via after an incomplete fill, so that some metal stays bare on the dielectric, is the residual-gap problem stated in this specification (paragraphs [0090]-[0096]). Neither Li nor Tien identifies that problem. Li has no hole and no gap. Tien's [0010] is to form the via so that "no voids will be generated." Combining them to recreate the applicant's gap-then-expand sequence is hindsight. MPEP 2142, 2143.01(III).
Fourth, the combination would change the principle of operation of each reference. Burying Li's free-standing package pillar in Tien's ILD removes the thermal-medium path and the package interconnect that Li is built around. Leaving a gap in Tien's via and oxidizing the fill undoes Tien's void-free three-layer etch method. A combination that requires each reference to stop doing what it teaches is not a reason to combine. MPEP 2143.01(VI).
Fifth, Wu (IDS) shows that ordinary skill already worked on tungsten contact gap-fill and residual voids. Wu's answer is better fill and CMP, not conversion of the contact metal into an oxide/nitride skin that closes a leftover gap while leaving bare metal on the dielectric. Wu therefore confirms the problem was known and points away from claim 15's chemical-expansion step as the solution.
The same gaps apply to Phoenix Pioneer, CN 111755409 A ("Phoenix"). Phoenix is a stacked package with pillar layers in molding. It does not supply a conversion skin plus bare metal-to-dielectric contact on the same pillar. Adding Phoenix to Li or Tien only restates a 3D package layout. It does not fix the sidewall structure of claim 1.
Claim 1 is therefore not anticipated by Li or by Tien, and is not obvious over Li in view of Tien, Tien in view of Li, or either combination further in view of Phoenix or Wu. Claims 2-10 and 12-14 inherit that structure. Claims 11 and 15-19 stand rejected only under 112(b) as set forth above; the same prior-art analysis applies to those claims once the 112 issues are corrected.
Conclusion
A shortened statutory period for reply is set to expire THREE MONTHS from the mailing date of this communication.
Claims 11 and 15-19 are rejected. Claims 1-10 and 12-14 are allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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21 September 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
1 Should Applicant later perfect a 119 claim, a certified copy of the foreign application must be in the file and, if the foreign application is not in English, a translation and a statement that the translation is accurate may be required. 37 CFR 1.55; MPEP 215-216. Until such a claim is perfected, the effective filing date remains April 20, 2022.
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