DETAILED ACTION
This Office Action is in response to an application that was filed on 10/10/2024. Claims 1-23 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings Objections
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s):
The limitation phrase “signal pin(s)” in the following limitations:
“a plurality of signal pins disposed at a first layer of the plurality of layers, each signal pin in the plurality of signal pins for coupling the integrated circuit package to a printed circuit board”.
“each respective signal trace being communicatively coupled to a respective signal pin of the plurality of signal pins”.
“and wherein the respective signal trace is communicatively coupled to the respective signal pin at a distal end of each branch”.
claimed in independent claim 1 needs to be shown in Figs. 1-3 in order to make structural relation with the other limitation structures, as detailed in the 112(a) and 112(b) rejections.
The limitation phrase “signal pin(s)” in the following limitations:
“providing an integrated circuit device package having a substrate comprising a plurality of layers and a plurality of signal pins disposed at a first layer of the plurality of layers and extending in a first direction orthogonal to a surface of the integrated circuit device package”.
“and for each respective signal pin of the plurality of signal pins: forming, in a second layer of the plurality of layers that is at least one layer above the first layer of the plurality of layers, a signal trace; forming, in a third layer of the plurality of layers that is at least one layer above the first layer of the plurality of layers, two branches of the signal trace, wherein a distal end of each branch is communicatively coupled to the signal pin”.
claimed in method independent claim 9 needs to be shown in Figs. 1-3 in order to make structural relation with the other limitation structures in the METHOD, as detailed in the 112(a) and 112(b) rejections.
The limitation phrase “signal pin(s)” in the following limitations:
“a plurality of signal pins disposed on a first layer of the plurality of layers”.
“each signal pin in the plurality of signal pins extending in a first direction orthogonal to the major plane”.
“and a plurality of signal traces, each respective signal trace being communicatively coupled to a respective signal pin of the plurality of signal pins”.
“wherein each respective signal trace bifurcates into two branches, a distal end of each branch being communicatively coupled to a respective signal pin”.
claimed in independent claim 18 needs to be shown in Figs. 1-3 in order to make structural relation with the other limitation structures, as detailed in the 112(a) and 112(b) rejections.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification Objections
The disclosure is objected to because of the following informalities:
One skilled in the arts would not have full appreciation of the invention since the specification does not clearly define how the structure of the “signal pin(s)” NOT having an ITEM DESIGNATION will meet the limitations in independent claims 1, 9, and 18, as indicated in the “Drawing Objection”. In addition, “signal pin(s)” is indicated in “SUMMARY” but NOT depicted in “DETAILED DESCRIPTION” in relation to Figs. 1-3 to support the claims.
Appropriate correction is required as well as no new matter should be entered.
Claim Objections
The disclosure is objected to because of antecedent errors:
The limitation phrase “printed circuit board” in the limitation “a printed circuit board having major plane and comprising at least one trace communicatively coupled to a respective solder ball of a ball grid array” does not have the proper antecedent basis in independent claim 18, since the limitation phrase “a printed circuit board” in the limitation “An apparatus configured to optimize data transmission rates between an integrated circuit package and a printed circuit board” has already established the proper antecedent basis.
Appropriate correction is required as well as no new matter should be entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-23 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, because the Specification and the Drawings do not provide enablement support in the limitations in claims. The Drawings in conjunction with the Specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make or use the invention commensurate in scope in the claim. See MPEP § 2166 and § 2164.
Independent claim 1 recites the limitation phrase “signal pin(s)” in the following limitations, where the cited limitation phrase has an ENABLING issue within the claim:
“a plurality of signal pins disposed at a first layer of the plurality of layers, each signal pin in the plurality of signal pins for coupling the integrated circuit package to a printed circuit board”.
“each respective signal trace being communicatively coupled to a respective signal pin of the plurality of signal pins”.
“and wherein the respective signal trace is communicatively coupled to the respective signal pin at a distal end of each branch”.
Though the cited limitation phrase is supported in the “SUMMARY” of the specification, there is NO ENABLEMENT in the cited limitation phrase in the “DETAILED DESCRIPTION” in RELATION to Figs. 1-3. Specifically, there is NO DETAILS in “DETAILED DESCRIPTION” of the specification, since “signal pin(s)” does NOT have an ITEM DESIGNATIONS in Figs. 1-3. Then HOW can the “signal pin(s)” have a positional relationship with the “first layer 102” and coupling the “integrated circuit package 104 to the printed circuit board 106” to MEET the cited limitation in claim 1 if there is in NO ITEM DESIGNATIONS in Figs. 1-3 for “signal pin(s)”. Consequently, any person skilled in the art to which it pertains, would have an ENABLEMENT issue with the claim since there is NO structural limitations in relation to Figs. 1-3 that details the limitation in relation to “signal pin(s)”.
Claim 2-8 are rejected since base claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph.
Method Independent claim 9 recites the limitation phrase “signal pin(s)” in the following methods steps, where the cited limitation phrase has an ENABLING issue within the claim:
“providing an integrated circuit device package having a substrate comprising a plurality of layers and a plurality of signal pins disposed at a first layer of the plurality of layers and extending in a first direction orthogonal to a surface of the integrated circuit device package”.
“and for each respective signal pin of the plurality of signal pins: forming, in a second layer of the plurality of layers that is at least one layer above the first layer of the plurality of layers, a signal trace; forming, in a third layer of the plurality of layers that is at least one layer above the first layer of the plurality of layers, two branches of the signal trace, wherein a distal end of each branch is communicatively coupled to the signal pin”.
Though the cited limitation phrase is supported in the “SUMMARY” of the specification, there is NO ENABLEMENT in the cited limitation phrase in the “DETAILED DESCRIPTION” in RELATION to Figs. 1-3. Specifically, there is NO DETAILS in “DETAILED DESCRIPTION” of the specification, since “signal pin(s)” does NOT have an ITEM DESIGNATIONS in Figs. 1-3. Then HOW can the “signal pin(s)” provide the method with a positional relationship with the “disposed at the first layer 102”, “extending in a first direction orthogonal to a surface of the integrated circuit package 104”, and “coupling the two branches 118 and 120 of the signal trace 100” to MEET the cited method limitations in claim 9 if there is in NO ITEM DESIGNATIONS in Figs. 1-3 for “signal pin(s)”. Consequently, any person skilled in the art to which it pertains, would have an ENABLEMENT issue with the claim since there is NO structural limitations in relation to Figs. 1-3 that details the limitation in relation to “signal pin(s)”.
Claim 10-17 are rejected since base claim 9 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph.
Independent claim 18 recites the limitation phrase “signal pin(s)” in the following limitations, where the cited limitation phrase has an ENABLING issue within the claim:
“a plurality of signal pins disposed on a first layer of the plurality of layers”.
“each signal pin in the plurality of signal pins extending in a first direction orthogonal to the major plane”.
“and a plurality of signal traces, each respective signal trace being communicatively coupled to a respective signal pin of the plurality of signal pins”.
“wherein each respective signal trace bifurcates into two branches, a distal end of each branch being communicatively coupled to a respective signal pin”.
Though the cited limitation phrase is supported in the “SUMMARY” of the specification, there is NO ENABLEMENT in the cited limitation phrase in the “DETAILED DESCRIPTION” in RELATION to Figs. 1-3. Specifically, there is NO DETAILS in “DETAILED DESCRIPTION” of the specification, since “signal pin(s)” does NOT have an ITEM DESIGNATIONS in Figs. 1-3. Then HOW can the “signal pin(s)” be “disposed on the first layer 102”, “extending the first direction orthogonal to the major plane”, “communicatively coupled to the respective signal trace 100”, and coupling the “communicatively coupled to each branch 118 and 120 that results from bifurcating the signal trace 100” to MEET the cited limitation in claim 18 if there is in NO ITEM DESIGNATIONS in Figs. 1-3 for “signal pin(s)”. Consequently, any person skilled in the art to which it pertains, would have an ENABLEMENT issue with the claim since there is NO structural limitations in relation to Figs. 1-3 that details the limitation in relation to “signal pin(s)”.
Claim 19-23 are rejected since base claim 18 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as the claims are incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2175 and § 2172.01.
Independent claim 1 recites the limitation phrase “signal pin(s)” in the following limitations, where the cited limitation phrase is CONFUSING within the claim:
“a plurality of signal pins disposed at a first layer of the plurality of layers, each signal pin in the plurality of signal pins for coupling the integrated circuit package to a printed circuit board”.
“each respective signal trace being communicatively coupled to a respective signal pin of the plurality of signal pins”.
“and wherein the respective signal trace is communicatively coupled to the respective signal pin at a distal end of each branch”.
Though the cited limitation phrase is supported in the “SUMMARY” of the specification, there is NO RELATION in the cited limitation phrase in the “DETAILED DESCRIPTION” in RELATION to Figs. 1-3. Specifically, there is NO DETAILS in “DETAILED DESCRIPTION” of the specification, since “signal pin(s)” does NOT have ANY RELATION to Figs. 1-3 with NO ITEM DESIGNATIONS. Then HOW can the “signal pin(s)” have a positional relationship with the “first layer 102” and coupling the “integrated circuit package 104 to the printed circuit board 106” to MEET the cited limitation in claim 1 if there is in NO ITEM DESIGNATIONS in Figs. 1-3 for “signal pin(s)” resulting in a GAP in the cited limitations. Consequently, there is NO structural relationship in the Specifications with Figs. 1-3 to support the cited limitations, since there is no ITEM DESIGNATION for “signal pin(s)” in Figs. 1-3. Therefore, one of ordinary skill in the art to which it pertains, would not be reasonably appraised of the scope of the invention given that the “signal pin(s)” will form a GAP with the other limitation structures in the cited limitations in conjunction with the Specifications and Figs. 1-3.
Claim 2-8 are rejected since base claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
Method Independent claim 9 recites the limitation phrase “signal pin(s)” in the following limitations, where the cited limitation phrase is CONFUSING within the claim:
“providing an integrated circuit device package having a substrate comprising a plurality of layers and a plurality of signal pins disposed at a first layer of the plurality of layers and extending in a first direction orthogonal to a surface of the integrated circuit device package”.
“and for each respective signal pin of the plurality of signal pins: forming, in a second layer of the plurality of layers that is at least one layer above the first layer of the plurality of layers, a signal trace; forming, in a third layer of the plurality of layers that is at least one layer above the first layer of the plurality of layers, two branches of the signal trace, wherein a distal end of each branch is communicatively coupled to the signal pin”.
Though the cited limitation phrase is supported in the “SUMMARY” of the specification, there is NO RELATION in the cited limitation phrase in the “DETAILED DESCRIPTION” in RELATION to Figs. 1-3. Specifically, there is NO DETAILS in “DETAILED DESCRIPTION” of the specification, since “signal pin(s)” does NOT have ANY RELATION to Figs. 1-3 with NO ITEM DESIGNATIONS. Then HOW can the “signal pin(s)” provide the method with a positional relationship with the “disposed at the first layer 102”, “extending in a first direction orthogonal to a surface of the integrated circuit package 104”, and “coupling the two branches 118 and 120 of the signal trace 100” to MEET the cited method limitations in claim 9 if there is in NO ITEM DESIGNATIONS in Figs. 1-3 for “signal pin(s)” resulting in a GAP in the cited method limitations. Consequently, there is NO structural relationship in the Specifications with Figs. 1-3 to support the cited method limitations, since there is no ITEM DESIGNATION for “signal pin(s)” in Figs. 1-3. Therefore, one of ordinary skill in the art to which it pertains, would not be reasonably appraised of the scope of the method invention given that the “signal pin(s)” will form a GAP with the other limitation structures in the cited method limitations in conjunction with the Specifications and Figs. 1-3.
Claim 10-17 are rejected since base claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
Independent claim 18 recites the limitation phrase “signal pin(s)” in the following limitations, where the cited limitation phrase is CONFUSING within the claim:
“a plurality of signal pins disposed on a first layer of the plurality of layers”.
“each signal pin in the plurality of signal pins extending in a first direction orthogonal to the major plane”.
“and a plurality of signal traces, each respective signal trace being communicatively coupled to a respective signal pin of the plurality of signal pins”.
“wherein each respective signal trace bifurcates into two branches, a distal end of each branch being communicatively coupled to a respective signal pin”.
Though the cited limitation phrase is supported in the “SUMMARY” of the specification, there is NO RELATION in the cited limitation phrase in the “DETAILED DESCRIPTION” in RELATION to Figs. 1-3. Specifically, there is NO DETAILS in “DETAILED DESCRIPTION” of the specification, since “signal pin(s)” does NOT have ANY RELATION to Figs. 1-3 with NO ITEM DESIGNATIONS. Then HOW can the “signal pin(s)” be “disposed on the first layer 102”, “extending the first direction orthogonal to the major plane”, “communicatively coupled to the respective signal trace 100”, and coupling the “communicatively coupled to each branch 118 and 120 that results from bifurcating the signal trace 100” to MEET the cited limitation in claim 18 if there is in NO ITEM DESIGNATIONS in Figs. 1-3 for “signal pin(s)” resulting in a GAP in the cited limitations. Therefore, one of ordinary skill in the art to which it pertains, would not be reasonably appraised of the scope of the invention given that the “signal pin(s)” will form a GAP with the other limitation structures in the cited limitations in conjunction with the Specifications and Figs. 1-3.
Claim 19-23 are rejected since base claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Contopanagos et al. (US20190393729A1 and Contopanagos hereinafter), as evidenced by Baroudi et al. (US20210167735A1 and Baroudi hereinafter), in view of Baroudi.
Regarding claim 1, Contopanagos discloses an integrated circuit package configured to optimize data transmission rates between the integrated circuit package and a printed circuit board (items 1504, 1516, 1518-1, 1518-2, 1502 of Fig. 15C and ¶[0333-0338] shows and indicates integrated circuit package 1504 {radiating element 1504 that includes an upper element 1516 and two lower elements 1518-1 and 1518-2; where antenna elements includes/comprised of conductive traces} configured to optimize data transmission rates by optimized radiation efficiency between integrated circuit package 1504 and printed circuit board 1502 {board comprised of substrate 1502}), comprising: a package substrate comprising a plurality of layers (items 1516, 1518-1, 1518-2 of Fig. 15C and ¶[0333-0336] shows and indicates package substrate 1516_1518-1_1518-2 {substrate formed by the layer of the upper element 1516 and the layers of the lower elements 1518-1 and 1518-2} comprising the plurality of layers 1516 & 1518-1_1518-2); a plurality of signal pins disposed at a first layer of the plurality of layers, each signal pin in the plurality of signal pins for coupling the integrated circuit package to a printed circuit board (items 1514-1, 1514-2, 1518-1, 1518-2 of Fig. 15C & items 1514-1, 1514-2 of Fig. 15B & items 1012, 1014 of Fig. 10A and ¶[0253_0334-0336 & 0338] shows and indicates the plurality of signal pins 1514-1 & 1514-2 {first feed 1514-1 and second feed 1514-2, where feeds are also referred to as pins such as first and second pins 1012,1014 that is also referred to as “feeds”, as shown in Fig. 10A and indicated in ¶[0253]} disposed at a first layer 1518-1_1518-2 of the plurality of layers 1516 & 1518-1_1518-2; where each signal pin 1514-1 OR 1514-2 in the plurality of signal pins 1514-1 & 1514-2 for coupling integrated circuit package 1504 to printed circuit board 1502); and a plurality of signal traces formed in one or more layers of the plurality of layers (items 1506, 1507, 1508 of Fig. 15B and ¶[0338-0339] is interpreted to show and indicate the plurality of signal traces 1506 & 1507 & 1508 {signal traces formed by the impedance transformer 1506, line 1507, and line 1508; where impedance transformer 1506, line 1507, and line 1508 can be form as traces, as evidenced by Baroudi in [0073] that indicates and shows impedance transformer traces 606, 608, and 610 of Fig. 6} formed in layer 1518-1_1518-2 of the plurality of layers 1516 & 1518-1_1518-2), each respective signal trace being communicatively coupled to a respective signal pin of the plurality of signal pins, wherein each respective signal trace bifurcates into two branches (Figs. 15B-15C and ¶[0336_0338-0339] shows and indicates where signal trace 1507 is communicatively coupled to signal pin 1514-1; and where signal trace 1508 is communicatively coupled to signal pin 1514-2, and where signal trace 1507 and signal trace 1508 bifurcates by splitting a single electrical pathway of signal trace 1506 into two or more separate paths such as into branch of trace 1507 and into branch of trace 1508), and wherein the respective signal trace is communicatively coupled to the respective signal pin at a distal end of each branch (Figs. 15B-15C and ¶[0336_0338-0339] shows and indicates where signal trace 1507 is communicatively coupled to signal pin 1514-1 and signal trace 1508 is communicatively coupled to signal pin 1514-2; and where signal pin 1514-1 is distal end of branch of trace 1507 from branch of trace 1508).
Contopanagos discloses the claimed invention except to explicitly disclose a plurality of signal traces.
Baroudi discloses a plurality of signal traces (items 606, 608, 610 of Fig. 6 and ¶[0073] shows and indicates a plurality of signal traces 606 & 608 & 610 {impedance transformers traces 606, 608 and 610}; therefore, the integrated circuit package of Contopanagos will have the following limitations by incorporating the trace structure of Baroudi: a plurality of signal traces formed in one or more layers of the plurality of layers; each respective signal trace being communicatively coupled to a respective signal pin of the plurality of signal pins; where each respective signal trace bifurcates into two branches; and where the respective signal trace is communicatively coupled to the respective signal pin at a distal end of each branch).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a plurality of signal traces into the structure of Contopanagos. One would have been motivated in the integrated circuit package of Contopanagos and have the plurality of signal traces, in order to have the freedom to design an integrated circuit package where various traces can be used to provide the desired phase shifts and/or impedance transformations to assist in providing differential feeds, as surreptitiously shown and described by Baroudi in Fig. 6 and ¶[0073], in the integrated circuit package of Contopanagos.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 18 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Zhang et al. (US20210272892A1 and Zhang hereinafter).
Regarding claim 18, Zhang discloses an apparatus configured to optimize data transmission rates between an integrated circuit package and a printed circuit board (items 500, 550, 502, 551 of Fig. 5 & item 351 of Fig. 3A and ¶[0018_0051 & 0070-0072] shows and indicates apparatus 500 {semiconductor packaged assembly 500} configured to optimize data transmission rates {by reduce the crosstalk in the differential vertical pins and/or interconnects to optimize the speed scaling in the peripheral component(s)} between integrated circuit package 550_502 {integrated circuit formed by socket 550 and second substrate 502} and printed circuit board 551/351 {second package substrate 551; package substrate 351}), comprising: the printed circuit board having major plane and comprising at least one trace communicatively coupled to a respective solder ball of a ball grid array (items 352, 333 of Fig. 3A and ¶[0051] shows and indicates where printed circuit board 351 has major plane and is comprised trace board-trace-352 {conductive pads 352 that is interpreted as trace} communicatively coupled to the respective solder ball 333 of the ball grid array); and an integrated circuit package configured to interface with the printed circuit board using the ball grid array (item 533 of Fig. 5 and ¶[0071] shows and indicates integrated circuit package 550_502 configured to interface with printed circuit board 551 using the ball grid array of solder balls 533), the integrated circuit package comprising: a package substrate comprising a plurality of layers, a plurality of signal pins disposed on a first layer of the plurality of layers, each signal pin in the plurality of signal pins extending in a first direction orthogonal to the major plane (items 508, 539a-c, 532 of Fig. 5 and ¶[0070 & 0072] shows and indicates integrated circuit package 550_502 is comprised of package substrate 508_539a-c {package substrate formed by base layer 508 and conductive layers 539a-c} that comprises plurality of layers 508 & 539a-c; where plurality of signal pins 532 is disposed on first layer 539a-c of plurality of layers 508 & 539a-c; and where each signal pin 532 in the plurality of signal pins 532 extending in the first direction orthogonal to the major plane of printed circuit board 551); and a plurality of signal traces, each respective signal trace being communicatively coupled to a respective signal pin of the plurality of signal pins, wherein each respective signal trace bifurcates into two branches, a distal end of each branch being communicatively coupled to a respective signal pin (items 311a, 330b, 312b, 311b, 330a, 312a, 332 of Figs. 3A-3B & item 370 of Fig. 3B and ¶[0052 & 0056] shows and indicates a plurality of signal traces 311a_330b_312b & 311b_330a_312a {signal trace formed by conductive line 311a, pad 330b, and conductive line 312b; signal trace formed by conductive line 311b, pad 330a, and conductive line 312a}; where signal trace 311a_330b_312b is communicatively coupled to signal pin 332_330b {pin 332 coupled on pad 330b}; and where signal trace 311b_330a_312a is communicatively coupled to signal pin 332_330a {pin 332 coupled on pad 330a}; and where signal trace 311a_330b_312b bifurcates signal trace 311b_330a_312a into two branches {as shown in Fig. 3B} that is the distal end of each branch while communicatively coupled to the respective signal pin 332_330b and signal pin 332_330a {as shown in Fig. 3A}).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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