DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7 and 9-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al. US 2025/0253224 A1.
Regarding claims 1-7, 9 and 10, Li discloses:
A semiconductor device (Fig. 6 in view of Fig. 4A) comprising:
a first transistor (annotated Fig. 6 below; “A”) located in a capacitor region (Fig. 6);
a backside deep trench capacitor (“DTC”) located beneath the first transistor; and
a backside back-end-of-the-line (BEOL) structure (annotated Fig. 6 below; “B”) located beneath the backside deep trench capacitor, wherein the backside deep trench capacitor is electrically connected to a source/drain region of the first transistor by a combination of a second plate electrode interconnect structure (annotated Fig. 6 below; “C”), a first level metal structure (annotated Fig. 6; 556/M0), and a backside source/drain contact structure (annotated Fig. 6 below; “D”), and wherein a hybrid bonding interface is present between the second plate electrode interconnect structure and the first level metal structure (530 shown direct bonded with 501 as in process step of Fig. 7I para 0051; and similar to Fig. 4A para 0031).
ANNOTATED Fig. 6:
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(claim 2) Fig. 6; “DTC” shown with three layers inherently first/second electrodes and a capacitor dielectric in electrical contact with “C”.
(claim 3) Fig. 6; a first electrode plate interconnect structure (annotated Fig. 6 above; “E”).
(claim 4) Fig. 6; a semiconductor substrate (540); a multilayered dielectric structure (532).
(claim 5) Fig. 6; a frontside BEOL structure (520).
(claim 6) when Fig. 6 is viewed inverted.
(claim 7) Fig. 6; annotated Fig. 6 above; “D” shown in direct contact with S/D regions of “A”.
(claim 9) Fig. 4A; logic device region (outside of “in chip PMIC or Active PDN” region on right); a second transistor (shown at bottom right); a through via structure (436); a though-via interconnect structure (region of metal interconnections in IMD 432); a logic device first level metal structure (interconnect metal M6 in 420); a logic device backside source/drain contact structure (M0 though M5 connected to source/drain through MD contacts).
(claim 10) Fig. 4A; para 0031; hybrid bonding between 430 and 401/420.
Regarding claims 11-17, Li discloses:
A semiconductor device (Fig. 6 in view of Fig. 4A) comprising:
a first transistor (annotated Fig. 6 below; “A”) and a backside deep trench capacitor (“DTC”) located in a capacitor region (Fig. 6);
a second transistor (shown at bottom right) located in a logic device region (outside of “in chip PMIC or Active PDN” region on right) that is located adjacent to the capacitor region (“in chip PMIC or Active PDN” region) (Fig. 4A in view extension of Fig. 6); and
a backside back-end-of-the-line (BEOL) structure (annotated Fig. 6 below; “B”) located beneath the backside deep trench capacitor and beneath the second transistor, wherein the backside deep trench capacitor is electrically connected to a source/drain region of the first transistor by a combination of a second plate electrode interconnect structure (annotated Fig. 6 below; “C”), a first level metal structure (annotated Fig. 6; 556/M0) and a backside source/drain contact structure (annotated Fig. 6 below; “D”), and the backside BEOL structure is electrically connected to a source/drain region of the second transistor by a combination of a through via structure (436), a through-via interconnect structure (region of metal interconnections in IMD 432), a logic device first level metal structure (interconnect metal M6 in 420) and a logic device backside source/drain contact structure (M0 though M5 connected to source/drain through MD contacts), and wherein a hybrid bonding interface is present between the second plate electrode interconnect structure and the first level metal structure and between the through-via interconnect structure and the logic device first level metal structure (530 shown direct bonded with 501 as in process step of Fig. 7I para 0051; and similar to Fig. 4A para 0031).
ANNOTATED Fig. 6:
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(claim 12) Fig. 6; “DTC” shown with three layers inherently first/second electrodes and a capacitor dielectric in electrical contact with “C”.
(claim 13) Fig. 6; a first electrode plate interconnect structure (annotated Fig. 6 above; “E”).
(claim 14) Fig. 6; a semiconductor substrate (540); a multilayered dielectric structure (532).
(claim 15) Fig. 6; a frontside BEOL structure (520 similar to Fig. 4A; 420).
(claim 16) when Fig. 6 in view of Fig. 4A are viewed inverted.
(claim 17) Fig. 6; annotated Fig. 6 above; “D” shown in direct contact with S/D regions of “A”; and in view of Fig. 4A, similar logic device backside source/drain contact structure is in contact with the source/drain regions of the second transistor (Fig. 4A; transistor shown at bottom right).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li, as applied to claim 1 above, in view of Yan et al. US 2013/0015510 A1.
Regarding claims 8 and 18, Li does not disclose:
(claim 8) further comprising a semiconductor buffer layer located between the backside source/drain contact structure and the source/drain of the first transistor; and (claim 18) further comprising a semiconductor buffer layer located beneath the source/drain region of the first transistor and the source/drain region of the second transistor.
Yan discloses a publication from a similar field of endeavor in which:
further comprising a semiconductor buffer layer (14) located between source/drain contact structure (18) and the source/drain (2/3) of the first transistor (Fig. 8).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the buffer layer taught by Yan between the backside source/drain contact structure and the source/drain of the first/second transistor of Li to prevent the metal Cu filled subsequently from diffusing into the device region, which may degrade the device performance. At the same time, the metal barrier layer can improve the adhesion between the subsequently filled metal and the substrate material (see Yan; para 0056).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
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/ERROL V FERNANDES/Primary Examiner, AU 2893
