DETAILED ACTION
This action is responsive to the pending claims, 1-20, received 10 October 2024. Accordingly, the detailed action of claims 1-20 is as follows:
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/10/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 9, 11, 13, 15-16 rejected under 35 U.S.C. 103 as being unpatentable over Bang et al (US 20190074053 A1, hereafter referred to as Bang) in view of Parikh et al (US 20150006140 A1, hereafter Parikh).
Regarding claim 1, Bang teaches a storage processing unit comprising: a first interface circuit configured to connect to a host server (Bang [0034] teaches a host interface connecting a storage device host and supplying power to the storage device via the interface) and receiving power (Bang [0034] teaches the host interface supplies power to the storage device) and one or more control signals from the host server when the host server is operating normally (Bang [0032] teaches the host controls a data processing operation of the first storage device, wherein instructions and data are exchanged between the host and storage device via the host interface [0035]), the first interface circuit being in a first clock domain in the storage processing unit (Bang [0068] teaches clocks supplied to a clock domain when power is supplied from the host such that the storage device belongs to a clock domain and users power and a clock supplied for the domain [0066-0068]);
a second interface circuit configured to connect to a storage device (Bang [0045, 0171] teaches a memory including a plurality of memory channels, as logical devices [0048], which connect to the memory to control the transmission of instructions or data [0048, 0171]);
a processing system coupled to the first interface circuit and the second interface circuit (Bang [0042] teaches a plurality of processing cores which perform operations of the first storage device in the first storage device including operations correspond to a command transmitted from the host [0034]) and configured to provide the host server with storage services (Bang [0042] teaches performing operations corresponding to data processing commands transmitted by the host such that the processing cores exchange data and commands with the host via the host interface) for a plurality of storage volumes, the processing system being in a second clock domain of the storage processing unit (Bang [0060] teaches the first storage device belonging to a clock domain wherein the storage device operates in the lower power mode when the power is not supplied from the host resulting in a different clock being supplied with a low frequency corresponding to the low power [0068]);
a backup power unit coupled to provide power (Bang [0054-0055] teaches an additional power module to supply power when power supplied by the host is insufficient or disconnected from the storage device) to the second clock domain when the host server fails to provide power through the first interface circuit (Bang [0014] teaches a lower clock frequency than when the power is supplied from the host such that a different clock is supplied with a low frequency corresponding to the low power when power is not supplied from the host [0068]).
However, Bang does not explicitly teach the storage volumes as virtual storage volumes.
Parikh, in an analogous art, teaches the storage volumes as virtual storage volumes (Parikh [0029] teaches datastores as virtualized representations of storage facilities) such that Parikh teaches a processing system coupled to a first interface circuit and second interface circuit (Parikh [0029] teaches a managing module which manages operations the storage including access by host computers to the datastores of storage pods) and configured to provide the host server with storage services for a plurality of virtual storage volumes (Parikh [0029] teaches the hosts accessing the storage device comprised of datastore and pods).
It would have been obvious for a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify Bang in view of Parikh in order to configure the plurality of storage volumes, as taught by Bang, include a plurality of virtual storage volumes, as taught by Parikh.
KSR rationale, B simple substitution of one known element (storage volumes as taught by Bang) for another known element (virtual storage volumes as taught by Parikh) in order to yield predictable results (access to storage by the host computer) supports the conclusion of obviousness.
Regarding claim 2, Bang-Parikh teaches the limitations of claim 1, as rejected above.
Additionally, Bang teaches the storage processing unit wherein the second clock domain operates on the power from the backup power unit when the first interface circuit is not receiving power from the host server (Bang [0166-0167 and 0172-0173] teaches using a clock of a lower frequency when there is no power supplied from the host).
Regarding claim 3, Bang-Parikh teaches the limitations of claim 1, as rejected above.
Additionally, Bang teaches the storage processing unit wherein the backup power unit comprises a battery (Bang [0055]).
Regarding claim 4, Bang-Parikh teaches the limitations of claim 1, as rejected above.
Additionally, Bang teaches the storage processing unit further comprising a connector configured for installation of the storage processing unit as a resident with the host server (Bang [0038] teaches the storage device connects into a slot in peripheral interface).
Regarding claims 9 and 11, they do not teach or further limit over the limitations presented above with respect to claims 1 and 2.
Therefore, claims 9 and 11 are rejected for the same reasons set forth above regarding claims 1 and 2.
Regarding claims 13 and 15, they do not teach or further limit over the limitations presented above with respect to claims 9 and 11
Therefore, claims 13 and 15 are rejected for the same reasons set forth above regarding claims 9 and 11.
Regarding claim 16, Bang-Parikh teaches the limitations of claim 13, as rejected above.
Additionally, Bang teaches the method further comprising installing the storage processing unit as a resident with the host server through a connector (Bang [0038] teaches the storage device connects into a slot in peripheral interface).
Claims 7, 19 rejected under 35 U.S.C. 103 as being unpatentable over Bang et al (US 20190074053 A1, hereafter referred to as Bang) in view of Parikh et al (US 20150006140 A1, hereafter Parikh) as applied above regarding claim 1, further in view of Kulshreshtha et al (US 10601683 B1, hereafter referred to as Kulshreshtha).
Regarding claim 7, Bang-Parikh teaches the limitations of claim 1, as rejected above.
Bang-Parikh, in an analogous art, teaches the storage processing unit wherein the first interface circuit is configured to interface with the host server via a Peripheral Component Interconnect Express (PCIe) bus (Bang [0038]).
However, Bang-Parikh does not explicitly teach the second interface circuit is configured to communicate with the storage device using Non-Volatile Memory Express (NVMe) or Serial Attached SCSI (SAS) protocols.
Kulshreshtha, in an analogous art, teaches the second interface circuit is configured to communicate with the storage device using Non-Volatile Memory Express (NVMe) or Serial Attached SCSI (SAS) protocols (Kulshreshtha [15:16-21] teaches the storage controller interfaces with the storage units via SAS).
It would have been obvious for a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify Bang-Parikh in view of Kulshreshtha in order to configure the second interface to communicate with the storage device, as taught by Bang-Parikh, communicate with NVMe or SAS protocols, as taught by Kulshreshtha.
KSR rationale, B simple substitution of one known element (protocol to communicate with the storage devices, as taught by Bang) for another known element (SAS protocol to communicate with the storage devices, as taught by Parikh) in order to yield predictable results (access to storage by the host computer through the protocol of the second interface circuit) supports the conclusion of obviousness.
Regarding claim 19, it does not teach or further limit over the limitations presented above with respect to claim 7.
Therefore, claim 19 is rejected for the same reasons set forth above regarding claim 7.
Claims 8, 10, 14, 20 rejected under 35 U.S.C. 103 as being unpatentable over Bang et al (US 20190074053 A1, hereafter referred to as Bang) in view of Parikh et al (US 20150006140 A1, hereafter Parikh) as applied above regarding claim 1, further in view of Yu et al (US 20160070474 A1, hereafter referred to as Yu).
Regarding claim 8, Bang-Parikh teaches the limitations of claim 1, as rejected above.
However, Bang-Parikh does not explicitly teach the storage processing unit wherein the backup power unit is configured to activate a smart power management mode to selectively reduce power consumption by disabling non-essential functions of the SPU during extended power outages.
Yu, in an analogous art, teaches the storage processing unit wherein the backup power unit is configured to activate a smart power management mode to selectively reduce power consumption by disabling non-essential functions during extended power outages (Yu [0056] teaches, when preset, isolating unnecessary components so they do not receive backup power).
It would have been obvious for a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify Bang-Parikh in view of Yu in order to configure the SPU, as taught by Bang-Parikh, to have a configuration to selectively reduce power consumption by disabling non-essential functions during extended power outages, as taught by Yu.
One of ordinary skill in the art would have been motivated in order to extend the period of backup power for critical components (Yu [0056]).
Regarding claim 10, Bang-Parikh teaches the limitations of claim 9, as rejected above.
However, Bang-Parikh does not explicitly teach the processor wherein the one or more circuits are further to provide storage services using the backup power unit until the host server resumes normal operation or a safe shutdown is completed.
Yu, in an analogous art, teaches the processor wherein the one or more circuits are further to provide services using the backup power unit until the host server resumes normal operation or a safe shutdown is completed (Yu [0049] teaches using the battery or uninterruptible power supply to properly shut down).
It would have been obvious for a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify Bang-Parikh in view of Yu in order to configure the storage services using backup power, as taught by Bang-Parikh, to continue until a safe shutdown is completed, as taught by Yu.
One of ordinary skill would have been motivated according to the reasons set forth above regarding Yu and claim 8.
Regarding claim 14, it does not teach or further limit over the limitations presented above with respect to claim 10.
Therefore, claim 14 is rejected for the same reasons set forth above regarding claim 10.
Regarding claim 20, it does not teach or further limit over the limitations presented above with respect to claim 8.
Therefore, claim 20 is rejected for the same reasons set forth above regarding claim 8.
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Bang et al (US 20190074053 A1, hereafter referred to as Bang) in view of Parikh et al (US 20150006140 A1, hereafter Parikh) as applied above regarding claim 1, further in view of Suljic et al (US 20210034128 A1, hereafter referred to as Suljic).
Regarding claim 18, Bang-Parikh teaches the limitations of claim 13, as rejected above.
Additionally, Bang-Parikh teaches the method further comprising: executing data services during a failure of the host server while the storage processing unit operates on backup power (Bang [0076] teaches operations performed in a lower power mode while power is disconnected from the host).
However, Bang-Parikh does not explicitly teach the data services including one or more of data deduplication, compression, and encryption.
Suljic, in an analogous art, teaches method further comprising: executing data services including one or more of data deduplication, compression, and encryption (Suljic [0034] teaches the memory controller is responsible for operations including encryption).
It would have been obvious for a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify Bang-Parikh in view of Suljic in order to configure the data services executed during failure of the host server while the storage processing unit operations on backup power, as taught by Bang-Parikh, include one or more of data deduplication, compression, and encryption, as taught by Suljic.
KSR rationale, B simple substitution of one known element (refresh data operational services, as taught by Bang) for another known element (encryption data operational services, as taught by Parikh) in order to yield predictable results (execution of data services from a host, by a storage processing unit on corresponding storage) supports the conclusion of obviousness.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “a first interface circuit configured to connect…..a second interface circuit configured to connect……a processing system…..configured to provide…..a connector configured for installation…..a processing system further configured to execute data services….a backup power unit configured to activate……” in claims 1, 4, 6-8.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Allowable Subject Matter
Claims 5-6, 12 and 17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Flynn et al (CN 103262054 A);
Huang (US 20100226194 A1);
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEAN TOKUTA whose telephone number is (571)272-5145. The examiner can normally be reached M-TH 630-430.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brian Gillis can be reached at 5712727952. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
SHEAN TOKUTA
Primary Examiner
Art Unit 2446
/SHEAN TOKUTA/Primary Examiner, Art Unit 2419
Prosecution Insights