DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 9-11 and 12-17, 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/27/2026.
Claim 1-8 and 18 are pending.
Allowable Subject Matter
Claim 5 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 6-8, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwak (PGPUB 20200211618), hereinafter as Kwak.
Regarding claim 1, Kwak teaches a memory comprising:
a clock receiver (Fig 4, ICGC 31) configured to receive clocks (WCK, only one clock instead of a plurality of clocks, but it has been ruled that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.);
a first divider (Fig 4, FDC 32) configured to divide the clocks to generate divided multi-phase clocks (IWCK, QWCK, IWCKB, QWCKB);
a second divider (Fig 4, FDC 32) configured to redivide the divided multi-phase clocks to generate redivided multi-phase clocks (IWCK_SD, IWC_SDB, IWCKB_SD, IWCKB_SDB); and
a command address reception circuit (Fig 12, CGC 111) configured to receive a command and an address (Fig 12, CA<1:7>) by using the divided multi-phase clocks in a first mode, and receive the command and the address by using the redivided multi-phase clocks in a second mode (Fig 12, Fig 4 by MODE).
Regarding claim 2, Kwak teaches a frequency of the command and the address input to the memory in the first mode is twice a frequency of the command and the address input to the memory in the second mode ([0024] use clocks with frequency of CLK or twice of CLK).
Regarding claim 4, Kwak teaches a plurality of command address receivers configured to receive signals from a plurality of command address terminals; and a plurality of flip-flops configured to latch reception results of the command address receivers by using the divided multi-phase clocks in the first mode and by using the redivided multi-phase clocks in the second mode (Fig 15, buffer 1113).
Regarding claim 6, Kwak teaches a command address decoder (Fig 15, at least 1114) configured to decode the command and the address received by the command address reception circuit to generate internal command signals and internal address signals.
Regarding claim 7, Kwak teaches a latency control circuit (Fig 14, at least 1112) configured to operate in synchronization with one of the divided multi-phase clocks and perform a latency control operation on at least one of read and write operations for the memory.
Regarding claim 8, Kwak teaches a chip select signal receiver configured to receive a chip select signal from a chip select terminal (Fig 15, 1112); and a decoding activation signal generation circuit configured to generate a decoding activation signal for activating the command address decoder by using the chip select signal (Fig 15, 1114 is activated by output of 1112).
Regarding claim 18, Kwak teaches the latency control circuit performs the latency control operation based on the internal command signals and the internal address signals (Fig 15).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwak, in view of Ooishi et al. (PGPUB 20030103407), hereinafter as Ooishi.
Regarding claim 3, Kwak teaches a memory as in rejection of claim 2,
But not expressly burst length in different mode,
Ooishi teaches in the first mode, 2N data terminals of the memory, where N is an integer of 1 or more, are connected to a memory controller, and a burst length for data transmitted and received through the 2N data terminals is set to M, where M is an integer of 1 or more, and in the second mode, N data terminals of the memory are connected to the memory controller and the burst length for data transmitted and received through the N data terminals is set to 2M (Table 1, burst length DDR mode 2/4/8 while SDR mode burst length 1/2/3).
Since Ooishi and Kwak are both from the same field of semiconductor memory device, the purpose disclosed by Ooishi would have been recognized in the pertinent art of Kwak.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to use different burst length as that of Ooishi in the device of Kwak for the purpose of managing a memory device according the mode selected.
Kim PGPUB 20020060949 also discloses features of claim 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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/MIN HUANG/ Primary Examiner, Art Unit 2827
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