DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maeda (U.S. Patent Publication No. 2014/0290997).
Regarding claim 1, in Figure 10, Maeda discloses an interconnect substrate comprising: a first interconnect layer (41); an insulating layer (33) formed on the first interconnect layer and containing a filler (paragraphs [0036] and [0038]); a via hole (43) penetrating the insulating layer and reaching an upper surface of the first interconnect layer; and a second interconnect layer (44) filling the via hole and electrically connected to the first interconnect layer, the second interconnect layer extending from inside the via hole and along an upper surface of the insulating layer (via conductor 44 extends along a small portion of the upper surface of lower insulating layer 51), wherein the insulating layer includes a first insulating layer (51) covering the first interconnect layer and a second insulating layer (52) laminated on the first insulating layer, the second insulating layer is thinner than the first insulating layer (Figure 10), an amount of the filler contained in the second insulating layer is smaller than an amount of the filler contained in the first insulating layer (the grain diameter of the inorganic material in the lower insulating layer 51 is decreased, allowing the lower insulating layer 51 to contain an increased amount of the inorganic material, paragraphs [0008], [0054], [0059]), in cross-sectional view, an inner surface of the via hole is inclined relative to a direction perpendicular to the upper surface of the first interconnect layer (Figure 10), in the cross-sectional view, an angle of the inner surface of the via hole in the first insulating layer with respect to the upper surface of the first interconnect layer is larger than an angle of the inner surface of the via hole in the second insulating layer with respect to the upper surface of the first interconnect layer (Similar to Figure 1B of the claimed invention: the angle α [let’s call it α], is between the bottom side surface of via conductor 44 and top surface of conductor layer 41; the angle β [let’s call it β], is the angle between the inclined side surface of via conductor 44 that intersects at the upper surface of lower insulating layer 51 and the upper surface of lower insulating layer 51; α ˃ β).
Regarding claim 2, Maeda discloses wherein a thickness of the second insulating layer is 1 μm or more and 2 μm or less (paragraph [0014]).
Regarding claim 3, Maeda discloses wherein a roughness of an upper surface of the second insulating layer is 250 nm or more and 300 nm or less in terms of an arithmetic average roughness Ra (paragraph [0038]).
Regarding claim 4, Maeda discloses wherein an amount of the filler contained in the first insulating layer is 70 wt% or more (paragraph [0012]).
Regarding claim 5, Maeda discloses wherein in the cross-sectional view, the angle of the inner surface of the via hole in the first insulating layer with respect to the upper surface of the first interconnect layer is from 70 degrees to 90 degrees, and the angle of the inner surface of the via hole in the second insulating layer with respect to the upper surface of the first interconnect layer is from 30 degrees to 60 degrees (Figure 10).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Prosecution Insights