DETAILED ACTION
This office action is in response to the application filed on 10/11/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/15/2025 and 11/05/2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1, 3-4, 6 and 13-14 objected to because of the following informalities: See table. Appropriate correction is required.
Claim; lines
Recite
Should be
1; 5-6
an extending direction
the extending direction
1; 6, 12 and 14
electric power
the electric power
3; 7
the multiple upper switch
multiple upper switch
3; 7
the multiple lower switch
multiple lower switch
4; 2
upper switch component
uppers switch components
4; 2
lower switch component
lower switch components
6; 6
phase same
same phase
13; 4, 13 and 16
electric power
the electric power
14; 3, 8 and 10
electric power
the electric power
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 11-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamaguchi US 2012/0106220.
Regarding Claims 1 and 14, Yamaguchi teaches (Figures 1-5) a power conversion device (Fig. 1) configured to convert electric power (from 12), the power conversion device comprising: a high potential conductor (BP) that is on a high potential side (positive side), extends in an extending direction (length direction), and to which electric power is to be supplied (at 10); a low potential conductor (Bn) that is on a low potential side (negative side), extends in an extending direction (length direction) along the high potential conductor, and to which electric power is to be supplied (toward 10); an output conductor (Bo) that extends in the extending direction (length direction) along the high potential conductor and the low potential conductor (see fig. 1) and configured to output electric power (sent to 10); an upper switch component (plural Swp) that is on the high potential side (positive side) and configured to perform switching to convert electric power (with on and off states); a lower switch component (plural Swn) that is on the low potential side (negative side) and configured to perform switching to convert electric power; and a capacitor component (SC) that is electrically connected in parallel to the upper switch component and the lower switch component (see fig. 1), wherein the upper switch component and the lower switch component are connected to the output conductor (swp and swn) at positions spaced apart (see fig. 2) from each other in the extending direction such that an output current flows through the output conductor (Ia or Ib) from the upper switch component toward the lower switch component in the extending direction (par. 40), the capacitor component and the upper switch component (swp and sc) are connected to the high potential conductor (Bp) such that, in an overlap region (e.g. 20) overlapping the output current in the extending direction (at Lo, see fig. 2), a high potential current flows through the high potential conductor from the capacitor component toward the upper switch component in a reverse direction to the output current (par .47), and the lower switch component and the capacitor component (swn and sc) are connected to the low potential conductor (bn) such that, in the overlap region (20), a low potential current flows through the low potential conductor from the lower switch component toward the capacitor component in a reverse direction to the output current (par .47). (For example: Par. 40-50)
Regarding Claim 11, Yamaguchi teaches (Figures 1-5) wherein multiple high potential conductors (Bp for each phase), multiple low potential conductors (Bn for each phase), and multiple output conductors (Bo) are provided, the upper switch component (Swp) is connected to each of the multiple high potential conductors and connected to each of the multiple output conductors (see fig. 1), the lower switch component (swn) is connected to each of the multiple output conductors and connected to each of the multiple low potential conductors (see fig. 1), and the capacitor component (Sc) is connected to each of the multiple high potential conductors and connected to each of the multiple low potential conductors (see fig. 1). (For example: Par. 40-50)
Regarding Claim 12, Yamaguchi teaches (Figures 1-5) further comprising: an upper and lower arm circuit (u phase arm) electrically connected between the high potential conductor and the low potential conductor (bp and bn), wherein the upper switch component includes an upper arm switch (swp) provided in an upper arm of the upper and lower arm circuit (see fig. 1), and the lower switch component includes a lower arm switch (swn) provided in a lower arm of the upper and lower arm circuit (see fig. 1). (For example: Par. 40-50)
Regarding Claim 13, Yamaguchi teaches (Figures 1-5) a power conversion device (Fig. 1) configured to convert electric power (from 12), the power conversion device comprising: a high potential conductor (Lp) that is on a high potential side (positive side), extends in an extending direction (length direction), and to which electric power is to be supplied (at 10); a low potential conductor (Ln) that is on a low potential side (negative side), extends in an extending direction (length direction) along the high potential conductor, and to which electric power is to be supplied (toward 10); an output conductor (Lo) that extends in the extending direction (length direction) along the high potential conductor and the low potential conductor (see fig. 1) and configured to output electric power (sent to 10); an upper switch component (swp) that includes an upper input terminal (24p) connected to the high potential conductor (Lp) and an upper output terminal (34p) connected to the output conductor (Lo) and configured to perform switching to convert electric power (on and off states); a lower switch component (swn) that includes a lower input terminal (34n) connected to the output conductor (Lo) and a lower output terminal (24n) connected to the low potential conductor (Ln) and configured to perform switching to convert electric power (on and off states); and a capacitor component (at Sc) that includes a high capacitor terminal (32p) connected to the high potential conductor (Lp) and a low capacitor terminal (32n) connected to the low potential conductor (Ln) and electrically connected in parallel to the upper switch component and the lower switch component (Fig. 1), wherein the upper output terminal (34p) and the lower input terminal (34n) are connected to the output conductor (Lo) at positions spaced apart from each other in the extending direction (see fig. 2), the upper input terminal (24p) and the high capacitor terminal (32p) are connected to the high potential conductor (Lp) such that at least one of the upper input terminal and the high capacitor terminal (32p) is positioned between the upper output terminal (34p) and the lower input terminal (34n) and that the upper input terminal and the high capacitor terminal are spaced apart in the extending direction (fig. 2), and the lower output terminal (24n) and the low capacitor terminal (32n) are connected to the low potential conductor (Ln) such that at least one of the lower output terminal and the low capacitor terminal (32n) is positioned between the upper output terminal (34p) and the lower output terminal (24n) and that the lower output terminal and the low capacitor terminal are spaced apart in the extending direction (see fig. 2). (For example: Par. 40-50)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi in view of Kimura US 2018/0269799.
Regarding Claim 2, Yamaguchi teaches (Figures 1-5) the device.
Yamaguchi does not teach wherein multiple upper switch components included in one phase and multiple lower switch components included in the one phase are arranged in the extending direction along the high potential conductor, the low potential conductor, and the output conductor.
Kimura teaches (Figure 1) wherein multiple upper switch components (22-23) included in one phase (U phase) and multiple lower switch components (22-23) included in the one phase are arranged in the extending direction (length direction) along the high potential conductor (11H), the low potential conductor (11L), and the output conductor (12). (For example: Par. 46-49)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamaguchi to include wherein multiple upper switch components included in one phase and multiple lower switch components included in the one phase are arranged in the extending direction along the high potential conductor, the low potential conductor, and the output conductor, as taught by Kimura to effectively reducing a switching loss.
Claim(s) 3-4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi in view of Mukunoki US 2016/0013706.
Regarding Claim 3, Yamaguchi teaches (Figures 1-5) the device.
Yamaguchi does not teach further comprising: a case including an outer peripheral wall in a ring shape and extending in a circumferential direction that is the extending direction, wherein the high potential conductor, the low potential conductor, and the output conductor extend in the circumferential direction along an inner peripheral surface of the outer peripheral wall, and the multiple upper switch components included in one phase and the multiple lower switch components included in the one phase are arranged in the circumferential direction along the inner peripheral surface.
Mukunoki teaches (Figure 1-2) further comprising: a case (at 1) including an outer peripheral wall (outside wall of 1) in a ring shape and extending in a circumferential direction that is the extending direction (see fig. 2), wherein the high potential conductor, the low potential conductor, and the output conductor (120, 130 and 110, output phases) extend in the circumferential direction along an inner peripheral surface of the outer peripheral wall (inside 11), and the multiple upper switch components (15a and 18a) included in one phase (U phase) and the multiple lower switch components (15b and 18b) included in the one phase are arranged in the circumferential direction along the inner peripheral surface (see fig. 2). (For example: Par. 25-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamaguchi to include further comprising: a case including an outer peripheral wall in a ring shape and extending in a circumferential direction that is the extending direction, wherein the high potential conductor, the low potential conductor, and the output conductor extend in the circumferential direction along an inner peripheral surface of the outer peripheral wall, and the multiple upper switch components included in one phase and the multiple lower switch components included in the one phase are arranged in the circumferential direction along the inner peripheral surface, as taught by Mukunoki to reduce electromagnetic noises in the system.
Regarding Claim 4, Yamaguchi teaches (Figures 1-5) the device.
Yamaguchi does not teach wherein the upper switch component and the lower switch component are located at a position spaced from the high potential conductor, the low potential conductor, and the output conductor, toward an outer side in a radial direction of the outer peripheral wall, and provided on the inner peripheral surface.
Mukunoki teaches (Figure 1-2) wherein the upper switch component and the lower switch component (with 151-163) are located at a position spaced from the high potential conductor, the low potential conductor, and the output conductor (110-130 and output conductor), toward an outer side in a radial direction of the outer peripheral wall (at 100), and provided on the inner peripheral surface (at 101). (For example: Par. 25-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamaguchi to include wherein the upper switch component and the lower switch component are located at a position spaced from the high potential conductor, the low potential conductor, and the output conductor, toward an outer side in a radial direction of the outer peripheral wall, and provided on the inner peripheral surface, as taught by Mukunoki to reduce electromagnetic noises in the system.
Regarding Claim 6, Yamaguchi teaches (Figures 1-5) wherein the overlap region (20) is a region extending in the extending direction to extend from a farthest upper component located farthest from the lower switch group among the upper switch components in the upper switch group to a farthest lower component located farthest from the upper switch group among the lower switch components in the lower switch group (see fig. 3a). (For example: Par. 40-50)
Yamaguchi does not teach further comprising: an upper switch group including multiple upper switch components that are included in one phase and are arranged in the extending direction; and a lower switch group aligned with the upper switch group in the extending direction and including multiple lower switch components that are included in the phase same as the multiple upper switch components in the upper switch group and are arranged in the extending direction.
Mukunoki teaches (Figure 1-2) further comprising: an upper switch group including multiple upper switch components (15a and 18a) that are included in one phase (Uphase) and are arranged in the extending direction (length direction); and a lower switch group (15b and 18b) aligned with the upper switch group in the extending direction and including multiple lower switch components (15b and 18b) that are included in the phase same as the multiple upper switch components in the upper switch group and are arranged in the extending direction (Fig. 2). (For example: Par. 25-33)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamaguchi to include further comprising: an upper switch group including multiple upper switch components that are included in one phase and are arranged in the extending direction; and a lower switch group aligned with the upper switch group in the extending direction and including multiple lower switch components that are included in the phase same as the multiple upper switch components in the upper switch group and are arranged in the extending direction, as taught by Mukunoki to reduce electromagnetic noises in the system.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi in view of Kadota US 2018/0183350.
Regarding Claim 7, Yamaguchi teaches (Figures 1-5) the device.
Yamaguchi does not teach further comprising: a first capacitor group including multiple first capacitor components, as the capacitor component, that are aligned with the upper switch component in an orthogonal direction orthogonal to the extending direction and arranged in the extending direction; and a second capacitor group including multiple second capacitor components, as the capacitor component, that are aligned with the lower switch component in the orthogonal direction and arranged in the extending direction, wherein the overlap region extends in the extending direction to extend from the first capacitor group to the second capacitor group.
Kadota teaches (Figures 1-6) further comprising: a first capacitor group including multiple first capacitor components (c2(c1), fig. 2), as the capacitor component, that are aligned with the upper switch component (at upper PM) in an orthogonal direction orthogonal to the extending direction and arranged in the extending direction (see fig. 2); and a second capacitor group (another C2(c1)) including multiple second capacitor components (see fig. 2), as the capacitor component, that are aligned with the lower switch component (at lower PM) in the orthogonal direction and arranged in the extending direction (see fig. 2), wherein the overlap region (LB) extends in the extending direction to extend from the first capacitor group to the second capacitor group (see fig. 2). (For example: Par. 47-55 and 69-75)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamaguchi to include further comprising: a first capacitor group including multiple first capacitor components, as the capacitor component, that are aligned with the upper switch component in an orthogonal direction orthogonal to the extending direction and arranged in the extending direction; and a second capacitor group including multiple second capacitor components, as the capacitor component, that are aligned with the lower switch component in the orthogonal direction and arranged in the extending direction, wherein the overlap region extends in the extending direction to extend from the first capacitor group to the second capacitor group, as taught by Kadota to provide a power conversion device which can be reduced in size while reducing a wiring inductance.
Regarding Claim 8, Yamaguchi teaches (Figures 1-5) the device.
Yamaguchi does not teach wherein the high potential conductor, the low potential conductor, and the output conductor are each formed in a plate shape, and plate surfaces of the high potential conductor, the low potential conductor, and the output conductor face one another.
Kadota teaches (Figures 1-6) wherein the high potential conductor, the low potential conductor, and the output conductor (Bp, Bn and Bac) are each formed in a plate shape (Fig. 4), and plate surfaces of the high potential conductor, the low potential conductor, and the output conductor face one another (Fig. 4). (For example: Par. 56-57)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamaguchi to include wherein the high potential conductor, the low potential conductor, and the output conductor are each formed in a plate shape, and plate surfaces of the high potential conductor, the low potential conductor, and the output conductor face one another, as taught by Kadota to provide a power conversion device which can be reduced in size while reducing a wiring inductance.
Regarding Claim 9, Yamaguchi teaches (Figures 1-5) the device.
Yamaguchi does not teach multiple plate-shaped conductors each of which has conductivity, formed in a plate shape, and stacked such that plate surfaces thereof face one another, wherein the multiple plate-shaped conductors include the high potential conductor, the low potential conductor, and the output conductor, and the output conductor is provided between a first plate portion and a second plate portion among the multiple plate-shaped conductors.
Kadota teaches (Figures 1-6) multiple plate-shaped conductors (Bp, Bn, Bm, Bac) each of which has conductivity, formed in a plate shape (see fig. 4), and stacked such that plate surfaces thereof face one another (Fig. 4), wherein the multiple plate-shaped conductors include the high potential conductor, the low potential conductor, and the output conductor, and the output conductor (Bp, Bn and Bac) is provided between a first plate portion and a second plate portion (see fig. 4b and 5b) among the multiple plate-shaped conductors. (For example: Par. 56-59 and 68)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Yamaguchi to include multiple plate-shaped conductors each of which has conductivity, formed in a plate shape, and stacked such that plate surfaces thereof face one another, wherein the multiple plate-shaped conductors include the high potential conductor, the low potential conductor, and the output conductor, and the output conductor is provided between a first plate portion and a second plate portion among the multiple plate-shaped conductors, as taught by Kadota to provide a power conversion device which can be reduced in size while reducing a wiring inductance.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi in view of Kadota US 2018/0183350 in view of Kashiwazaki JP 2019-110346 (US 2020/0395868 used for translation purposes).
Regarding Claim 10, Yamaguchi teaches (Figures 1-5) the device.
Yamaguchi does not teach wherein the multiple plate-shaped conductors include a ground conductor that extends in the extending direction along the high potential conductor, the low potential conductor, and the output conductor, and grounded, and the ground conductor is provided at least one of a pair of outermost positions in the multiple plate-shaped conductors.
Kashiwazaki teaches (Figures 1-2) wherein the multiple plate-shaped conductors (L conductors, fig. 1) include a ground conductor (Lg) that extends in the extending direction along the high potential conductor, the low potential conductor, and the output conductor, and grounded (see fig. 2), and the ground conductor is provided at least one of a pair of outermost positions in the multiple plate-shaped conductors (see fig. 2, at Lg and Le). (For example: Par. 22, 44 and 88)
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 5; prior art of record fails to disclose either by itself or in combination: “…an upper capacitor component, as the capacitor component, that is provided at a position aligned with the upper switch component in a radial direction of the outer peripheral wall and spaced from the upper switch component toward an inner side in the radial direction; and a lower capacitor component, as the capacitor component, that is provided at a position aligned with the lower switch component in the radial direction and spaced from the lower switch component toward the inner side in the radial direction, wherein the upper capacitor component and the lower capacitor component include a high capacitor terminal connected to the high potential conductor and a low capacitor terminal connected to the low potential conductor, and in one of the upper capacitor component and the lower capacitor component, the high capacitor terminal is provided on an outer side in the radial direction with respect to the low capacitor terminal, and in the other of the upper capacitor component and the lower capacitor component, the low capacitor terminal is provided on the outer side in the radial direction with respect to the high capacitor terminal.”
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/ Primary Examiner, Art Unit 2838
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