Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 14 and 18
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
The information disclosure statements (IDS) are submitted on 10/11/2024 and 5/4/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "the set of margin read reference" in second last line. There is insufficient antecedent basis for this limitation in the claim.
Claims 19-20 carry the same deficit due to dependency and henceforth rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kund et al. (US 20100058018) in view of Thiers et al. (US 20230072467).
Regarding independent claim 14, Kund discloses an integrated circuit (Figs. 1-8 and [0024] describes integrated circuit device 100), comprising:
a magnetoresistive random access memory (MRAM) (Fig. 1 and [0023] describes resistive memories such as MRAM);
a non-volatile memory (NVM) configured to store an indication of a target bit error rate and a set of margin read reference (Fig. 5B and [0044] describes ideal storage level values for representing the logical states, signal margins during read operations and bit errors) and temperature correlations for the target bit error rate (Fig. 6C and [0045] and [0047] describes that in operation 600, an elevated temperature condition causes a temperature sensor bit to be set to provide an indication to the memory scheduler. Upon the memory scheduler identifying suitable trigger condition(s) in operation 610 (e.g., idle mode, power up/down, battery charging, or other external trigger commands or signals), the memory scheduler can read the temperature bit (operation 620)); and
built-in self-test (BIST) circuitry (Figs. 4, 8 and [0064] describes BIST operation 810 is performed to identify defective memory cells. In decision block 820, if a failing cell is observed in the memory array (or sub-array) being tested) configured to perform temperature sensing by:
Further, Thiers teaches iteratively adjusting and using a margin read reference to obtain margin read data from the MRAM until a bit error rate of the MRAM achieves the target bit error rate, wherein each adjusted margin read reference is at a different offset from a normal read reference ([0044]-[0047] describes that total number of errors is a good measure to serve as a basis for read reference voltage calibration, as defined above, if there is a relatively large difference between the threshold for a first readout of the reference data and the optimal read threshold. And optimizing the determined new voltage level of the read reference voltage comprises: (i) Setting for the read reference voltage an associated target probability, e.g., a target probability ratio, for the asymmetry or symmetry, respectively, of 1-to-0 and 0-to-1 bit errors; (ii) Reading payload data from the NVM, decoding it, and determining a number of 1-to-0 bit errors and a number of 0-to-1 bit errors in the read payload data; and (iii) Modifying the new voltage level based on the determined numbers of 1-to-0 bit errors and 0-to-1 bit errors such as to cause the ratio of these numbers to approach the target probability), and
outputting a sensed temperature of the integrated circuit by using a resulting value of the iteratively adjusted margin read reference which resulted in the MRAM achieving the target bit error rate to calculate the sensed temperature ([0102] describes measurements of read disturb as well as cross-temperature effects were taken into account. For the read disturb, many read cycles were performed before the measurements).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Thiers to Kund in order to provide with improved approach for minimizing the bit error rate (BER) for readouts from NVM, such as flash memory as taught by Thiers ([0009]).
Regarding claim 15, Kund and Thiers together disclose all the elements of claim 14 as above and further the BIST circuitry calculates the sensed temperature corresponding to the resulting value of the iteratively adjusted margin read reference by interpolating between temperatures of the set of margin read reference and temperature correlations stored in the NVM (Figs. 4, 8 and [0064] of Kund and (0042], [0047] and [0102] of Thiers).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Thiers to modified Kund in order to provide with improved approach for minimizing the bit error rate (BER) for readouts from NVM, such as flash memory as taught by Thiers ([0009]).
Regarding claim 16, Kund and Thiers together disclose all the elements of claim 14 as above and further the BIST circuitry is configured to obtain the bit error rate of the MRAM after each adjustment of the margin read reference by comparing normal read data obtained from each address of a plurality of addresses using the normal read reference to margin read data obtained from each address of the plurality of addresses using the adjusted margin read reference (Figs. 4, 8 and [0064] of Kund and (0042], [0047] and [0102] of Thiers).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Thiers to modified Kund in order to provide with improved approach for minimizing the bit error rate (BER) for readouts from NVM, such as flash memory as taught by Thiers ([0009]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kund et al. (US 20100058018) in view of Thiers et al. (US 20230072467) and further in view of Bhattacharya et al. (US 7251574).
Regarding claim 17, Kund and Thiers together disclose all the elements of claim 14 as above and through Bhattacharya further the indication of the target bit error rate and the set of margin read reference and temperature correlations for the target bit error rate are stored in the NVM during production testing, prior to field operation of the integrated circuit (Figs. 3-4, 8 shows production test flow and corresponding sections of the specification discusses offset and BER).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Bhattacharya to modified Kund in order to provide with system and method for bit error rate testing of transceivers as taught by Bhattacharya ((2)).
Allowable Subject Matter
Claims 1-13 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Independent claim 1 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
“BIST circuitry comprising: an address sequencer configured to generate a sequence of addresses of the MRAM; and control circuitry configured to: select a current margin read reference, perform a sweep through the sequence of addresses using the current margin read reference wherein, at each address, the control circuitry is configured to direct a normal read from the address to obtain normal read data from the MRAM and a margin read from the address to obtain margin read data from the MRAM, obtain a bit error count for the sweep based on comparisons between the normal read data and the margin read data obtained at each address of the sequence of addresses, selectively modify the current margin read reference based on whether or not the bit error count achieves the target bit error rate”.
Conclusion
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 6/3/2026
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