DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 1: it appears that “programed” in line(s) 24 was meant to be -- programmed --.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wong (US 2020/0066351) in view of Aritome et al. (US 2012/0106260 “Aritome”), and further in view of Kim (US 2016/0293259).
The disclosure of fig(s). 1-12 of Wong is incorporated into an embodiment as considered below, since elements are analogous and similarly referenced [0110]. Therefore, before the effective filing date of the invention, it would have been obvious to one with ordinary skill in the art to modify the figure(s) with the embodiment as taught for the purpose of improving the overall performance by using adaptive programming to verify memory cells reaching a target level [0006+, 0110].
Regarding claim 1, Wong discloses a method of operating a semiconductor memory device including a plurality of program loops (“a series of one or more programming sequences” fig. 3A [0056]) for programming selected memory cells (i.e. of selected word lines; fig. 3A) among a plurality of memory cells (fig. 1, 2) to a first program state higher (601; fig. 6A-6B) than an erase state (600; fig. 6A-6B) and a second program state (602-615; fig. 6A-6B) higher than the first program state, wherein each of the plurality of program loops comprises (“each programming sequence, the memory cell is programmed and verified” [0056]):
applying a program voltage to a word line (“control circuit 125 drives a selected local word line 114 to a word line programming voltage” [0038], i.e. programing voltage 310-315/319; fig. 3A) connected to the selected memory cells (memory cells of selected word lines WL1, WL2; fig. 3A);
applying a verify voltage to a selected word line (“control circuit 125 lowers the selected local word line 114 to a verify word line voltage” [0038], i.e. verify voltage 320-323/326; fig. 3A) connected to the selected memory cells (memory cells of WL1, WL2);
comparing bit line currents (current of memory cell(s) coupled to column line(s); fig. 1, 2) corresponding to the selected memory cells and different reference currents (“compares the currents through a memory cell [i.e. bit line currents] and a first reference cell” and from a second or third reference cell [i.e. different reference currents] [0013]; fig. 12-14);
applying, based on a result of the comparing (fig. 12-14), a first voltage, a second voltage, a third voltage (claim 10), or a program prohibition voltage (a high level voltage to inhibit programming [0097], i.e. inhibit voltage; claim 10) greater than the third voltage (claim 11), to bit lines connected to first memory cells (CL1; fig. 3A), to bit lines connected to second memory cells (CL2; fig. 3A).
Wong does not expressly disclose a first program permission voltage, a second program permission voltage greater than the first program permission voltage, a third program permission voltage greater than the second program permission voltage, or a program prohibition voltage greater than the third program permission voltage to bit lines connected to first memory cells to be programmed to the first program state among the selected memory cells; and applying the first program permission voltage to bit lines connected to second memory cells to be programmed to the second program state among the selected memory cells when the first memory cells are programed.
Aritome discloses a first program permission voltage, a second program permission voltage greater than the first program permission voltage, a third program permission voltage greater than the second program permission voltage, or a program prohibition voltage greater than the third program permission voltage to bit lines connected to first memory cells to be programmed to the first program state among the selected memory cells (“a first program permission voltage may be supplied to the bit lines of memory cells, each having the threshold voltage lower than the second sub-verification voltage, a second program permission voltage higher than the first program permission voltage may be supplied to the bit lines of memory cells, each having the threshold voltage higher than the first sub-verification voltage, but lower than the target verification voltage, a third program permission voltage higher than the second program permission voltage may be supplied to the bit lines of the fast program memory cells, and a program inhibition voltage higher than the third program permission voltage may be supplied to the bit lines of memory cells, each having the threshold voltage higher than the target verification voltage” [0011]).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Wong is modifiable as taught by Aritome for the purpose of facilitating data accessing schemes by optimizing threshold voltage distributions [0068, 0082 of Aritome], which is common and well known in the art for preventing erroneous readouts from selected memory cells to secure the integrity of data storage.
Kim discloses applying the first program permission voltage (Vps; fig. 8, 10) to bit lines connected to second memory cells (MCG12 and/or MCG13, MCG14; fig. 8, 10) to be programmed to the second program state (S2, and or S3, S4, respectively; fig. 8) among the selected memory cells (i.e. of selected word line) when the first memory cells (MCG11 and/or MCG12; fig. 8, 10) are programed (programmed to first program state S1 and/or S2; fig. 8, 10).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Wong is further modifiable as taught by Kim for the purpose of facilitating data accessing schemes by optimizing threshold voltage distributions [0106 of Kim], which is common and well known in the art for preventing erroneous readouts from selected memory cells to secure the integrity of data storage.
Regarding claim 2, Wong discloses the method of claim 1, wherein the different reference currents include a first reference current, a second reference current less than the first reference current, and a third reference current less than the second reference current (first through third reference currents of reference cells having VCP6/VCP3/VCP1 (VCP5); fig. 12-14).
Regarding claim 3, Wong discloses the method of claim 2, wherein the first reference current is compared to the bit line currents, then the second reference current is compared to the bit line currents, and then the third reference current is compared to the bit line currents (fig. 12-14).
Regarding claim 4, Wong discloses the method of claim 1, wherein the verify voltage is applied to the selected word line during the comparing of the bit line currents and the different reference currents (fig. 13-14).
Regarding claim 5, Wong discloses the method of claim 2, wherein when the bit line currents are compared to the different reference currents, memory cells, among the first memory cells, which are connected to bit lines having a current greater than the first reference current, memory cells, among the first memory cells, which are connected to bit lines having a current between the first reference current and the second reference current, and memory cells, among the first memory cells, which are connected to bit lines having a current between the second reference current and the third reference current (fig. 12-14).
Aritome discloses are determined as first program permission cells, are determined as second program permission cells, are determined as third program permission cells (fig. 2-4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Wong is modifiable as taught by Aritome for the purpose of facilitating data accessing schemes by optimizing threshold voltage distributions [0068, 0082 of Aritome], which is common and well known in the art for preventing erroneous readouts from selected memory cells to secure the integrity of data storage.
Regarding claim 6, Aritome discloses the method of claim 5, wherein the first program permission voltage is applied to the bit lines connected to the first program permission cells, the second program permission voltage is applied to the bit lines connected to the second program permission cells, and the third program permission voltage is applied to the bit lines connected to the third program permission cells (fig. 2-4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Wong is modifiable as taught by Aritome for the purpose of facilitating data accessing schemes by optimizing threshold voltage distributions [0068, 0082 of Aritome], which is common and well known in the art for preventing erroneous readouts from selected memory cells to secure the integrity of data storage.
Conclusion
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/UYEN SMET/
[AltContent: connector] Primary Examiner, Art Unit 2824
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