CTNF 18/913,710 CTNF 91416 DETAILED ACTION As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Specification 06-16 AIA Applicant is reminded of the proper language and format for an abstract of the disclosure. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc. The first sentence of the abstract should be omitted. 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: -- WRITE LATENCY AND ENERGY CONSUMPTION USING ASYMMETRIC CELL DESIGN -- Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-36 AIA Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 11482284 B1 in view of Yamamoto, US 9595567 B2 . Claim 8 of US 11482284 B1 discloses a method of writing, thresholding concurrently, and further writing, but does not appear to disclose the details of each memory cell of the set of memory cells is coupled with a first access line via a first electrode having a first contact area and is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area. Yamamoto discloses the details of each memory cell of the set of memory cells (see Yamamoto Fig 7) is coupled with a first access line via a first electrode having a first contact area (see Yamamoto Fig 7 Ref 302; Examiner takes notice that interfacial electrodes between resistive memory layers and interconnects is common and well known. ) and is coupled with a respective second access line via a second electrode having a second contact area (see Yamamoto Fig 7 Ref 305) different than the first contact area (see Yamamoto Fig 7 Ref 33). It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a method, as disclosed by Claim 8 of US 11482284 B1, may be implemented in a particular device structure, as disclosed by Yamamoto. The inventions are well known variants of operations for resistive memories, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Yamamoto’s attempt to engineer the conductive area (see Yamamoto Cols 1-2, Lines 66-6) . 08-36 AIA Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 11848051 B2 in view of Yamamoto, US 9595567 B2 . Claim 8 of US 11848051 B1 discloses a method of writing, thresholding concurrently, and further writing, but does not appear to disclose the details of each memory cell of the set of memory cells is coupled with a first access line via a first electrode having a first contact area and is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area. Yamamoto discloses the details of each memory cell of the set of memory cells (see Yamamoto Fig 7) is coupled with a first access line via a first electrode having a first contact area (see Yamamoto Fig 7 Ref 302; Examiner takes notice that interfacial electrodes between resistive memory layers and interconnects is common and well known. ) and is coupled with a respective second access line via a second electrode having a second contact area (see Yamamoto Fig 7 Ref 305) different than the first contact area (see Yamamoto Fig 7 Ref 33). It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a method, as disclosed by Claim 8 of US 11482284 B1, may be implemented in a particular device structure, as disclosed by Yamamoto. The inventions are well known variants of operations for resistive memories, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Yamamoto’s attempt to engineer the conductive area (see Yamamoto Cols 1-2, Lines 66-6) . 08-36 AIA Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 21 of U.S. Patent No. 11482284 B1 in view of Yamamoto, US 9595567 B2 . Claim 21 of US 11482284 B1 discloses an apparatus of a set of memory cells with access lines and processing circuitry capable of writing, thresholding concurrently, and further writing, but does not appear to disclose the details of a first access line via a first electrode having a first contact area and is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area. Yamamoto discloses the details of each memory cell of a first access line via a first electrode having a first contact area (see Yamamoto Fig 7 Ref 302; Examiner takes notice that interfacial electrodes between resistive memory layers and interconnects is common and well known. ) and is coupled with a respective second access line via a second electrode having a second contact area (see Yamamoto Fig 7 Ref 305) different than the first contact area (see Yamamoto Fig 7 Ref 33). It would have been obvious to one skilled in the art at the time of the effective filing of the invention that an apparatus, as disclosed by Claim 21 of US 11482284 B1, may be implemented in a particular device structure, as disclosed by Yamamoto. The inventions are well known variants of operations for resistive memories, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Yamamoto’s attempt to engineer the conductive area (see Yamamoto Cols 1-2, Lines 66-6) . 08-36 AIA Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 21 of U.S. Patent No. 11482284 B1 in view of Yamamoto, US 9595567 B2 . Claim 21 of US 11482284 B1 discloses an apparatus of a set of memory cells with access lines and processing circuitry capable of writing, thresholding concurrently, and further writing, but does not appear to disclose the details of a first access line via a first electrode having a first contact area and is coupled with a respective second access line via a second electrode having a second contact area different than the first contact area. Yamamoto discloses the details of each memory cell of a first access line via a first electrode having a first contact area (see Yamamoto Fig 7 Ref 302; Examiner takes notice that interfacial electrodes between resistive memory layers and interconnects is common and well known. ) and is coupled with a respective second access line via a second electrode having a second contact area (see Yamamoto Fig 7 Ref 305) different than the first contact area (see Yamamoto Fig 7 Ref 33). It would have been obvious to one skilled in the art at the time of the effective filing of the invention that an apparatus, as disclosed by Claim 21 of US 11482284 B1, may be implemented in a particular device structure, as disclosed by Yamamoto. The inventions are well known variants of operations for resistive memories, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Yamamoto’s attempt to engineer the conductive area (see Yamamoto Cols 1-2, Lines 66-6) . Allowable Subject Matter Claim(s) 2-21 is/are objected to as being rejected under an obvious type double patenting, but would be allowable if a terminal disclaimer addressing the at issue patents were to be filed.. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The prior art does not appear to disclose (as recited in claim 2): thresholding, during the first portion of the access operation and concurrent with writing the first logic state to the first subset, memory cells of a second subset of the set of memory cells, the thresholding based at least in part on the second contact area being different than the first contact area; and writing, during a second portion of the access operation, a second logic state to the memory cells of the second subset based at least in part on the thresholding. The prior art does not appear to disclose (as recited in claim 9): threshold, during the first portion of the access operation and concurrent with writing the first logic state to the first subset, memory cells of a second subset of the set of memory cells, the thresholding based at least in part on the second contact area being different than the first contact area; and write, during a second portion of the access operation, a second logic state to the memory cells of the second subset based at least in part on the thresholding. The prior art does not appear to disclose (as recited in claim 15): threshold, during the first portion of the access operation and concurrent with writing the first logic state to the first subset, memory cells of a second subset of the set of memory cells, the thresholding based at least in part on the second contact area being different than the first contact area; and write, during a second portion of the access operation, a second logic state to the memory cells of the second subset based at least in part on the thresholding . 13-03 Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cheon, US 20170262171 A1 discloses thresholding, during the first portion of an access operation. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICHARD ELMS can be reached at (517)272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 04/22/2026 Application/Control Number: 18/913,710 Page 2 Art Unit: 2824 Application/Control Number: 18/913,710 Page 3 Art Unit: 2824 Application/Control Number: 18/913,710 Page 4 Art Unit: 2824 Application/Control Number: 18/913,710 Page 5 Art Unit: 2824 Application/Control Number: 18/913,710 Page 6 Art Unit: 2824 Application/Control Number: 18/913,710 Page 7 Art Unit: 2824 Application/Control Number: 18/913,710 Page 8 Art Unit: 2824 Application/Control Number: 18/913,710 Page 9 Art Unit: 2824 Application/Control Number: 18/913,710 Page 10 Art Unit: 2824
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