DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 8,670,265 to Deng (hereafter Deng) in view of US 11,087,835 to Akamatsu et al. (hereafter Akamatsu) .
Regarding independent claim 1, Deng teaches a unit cell circuit of a memory cell array, the unit cell circuit comprising:
a sub-cell array including a plurality of memory cells each connected to a supply line (FIG. 3: e.g. a sub-cell array comprising MCELL C00-C30 coupled to bit lines BL0-BLN0 and supply line 340); and
an assist circuit connected to the sub-cell array through the supply line (FIG. 3: power switch PSW 308) and configured to pre-charge the supply line with a supply voltage during a stand-by mode based on a control signal (FIGS. 9 and 6c: maintain supply line 340 at VDDL during RETAIN with PSZ inactive high)
Deng does not teach the strikethrough limitation.
Akamatsu teaches a memory cell connected to an assist circuit through a supply line (FIGS. 6-7: latch cell 52A coupled to an assist circuit 144A through dynamic voltage line VPERIZn); the assist circuit configured to block the supply line upon initiation of a write operation (see 7:50-65 and 8:15-57).
Since Deng and Akamatsu are both from the same field of endeavor, the purpose disclosed by Akamatsu would have been recognized in the pertinent art of Deng.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to block the supply line upon initiation of a write operation using word line signal as suggested by Akamatsu to the memory array of Deng in order to increasing the write assist power (see 8:41-47).
Regarding dependent claim 2, Deng teaches wherein the memory cell array comprises a plurality of unit cell circuits (see FIG. 3). Akamatsu teaches wherein a voltage of the supply line collapses from the supply voltage based on the assist circuit blocking the supply line during the write operation (FIG. 9: dynamic voltage line 160 collapsing during time period 168, see 7:50-65 and 8:15-57).
Regarding dependent claim 3, Akamatsu teaches wherein the voltage of the supply line stops collapsing based on the write operation on one of the plurality of memory cells succeeding (FIG. 9: dynamic voltage line 160 stop collapsing and starting raising after time period 168).
Regarding dependent claim 4, Akamatsu teaches wherein, the assist circuit is configured to: form a pull-up current on the supply line based on the collapsing of the voltage of the supply line after the initiation of the write operation (FIG. 9: dynamic voltage line 160 stop collapsing and starting raising after time period 168).
Regarding dependent claim 5, Deng teaches wherein the assist circuit includes: a first transistor having a gate configured to receive the control signal, a source configured to receive the supply voltage, and a drain connected to the supply line (PMOS 608 of FIG. 6a, OR PMOS 614 of FIG. 6c); and a second transistor having a gate configured to receive a logic high valued voltage during the write operation, a drain configured to receive the supply voltage, and a source connected to the supply line (PMOS 610 of FIG. 6a or PMOS 622 of FIG. 6c).
Regarding dependent claim 6, Deng teaches wherein the control signal is commonly applied to the gate of the first transistor and the gate of the second transistor (see FIG. 6a).
Regarding dependent claim 7, Deng teaches wherein the second transistor has its gate and its drain connected to each other (see FIG. 6c).
Regarding dependent claim 8, neither Deng nor Akamatsu teaches wherein the assist circuit includes: a stack transistor having a gate configured to receive a ground voltage and a drain connected to the supply line.
However, it would have been obvious to a person with ordinary skill in the art to realize that the recited stack transistor acts like a current limiter, which prevents overflowing of current to the memory cells.
Regarding dependent claim 9, Deng teaches wherein the assist circuit includes: a first transistor having a gate configured to receive the control signal, a source configured to receive the supply voltage, and a drain connected to the supply line; and a third transistor having a gate and a drain that are connected to the supply line and having a source configured to receive the supply voltage (see FIG. 6d).
Regarding dependent claim 10, Deng teaches wherein the control signal corresponds to a logic low value during the stand-by mode and corresponds to a logic high value during the write operation (see FIG. 5, 6c and 9).
Regarding dependent claim 11, Akamatsu teaches wherein each of the plurality of memory cells is selected through a word line during the write operation, and wherein the control signal transitions to a logic high value at a first timing when the word line is activated or at a second timing after a specific time period elapses (see 7:50-65 and 8:15-57).
Regarding dependent claim 12, Deng teaches wherein the supply line is configured for the sub-cell array through the assist circuit (see FIG. 3).
Regarding independent claim 13, Deng teaches a memory device comprising:
a memory cell array including a plurality of unit cell circuits (FIG. 3: columns of MCELL); and
a row peripheral circuit configured to control the plurality of unit cell circuits (FIG. 4: row decoder 114 for generating row select signal WWL/RWL),
wherein each of the plurality of unit cell circuits includes:
a respective sub-cell array including a respective plurality of memory cells (FIG. 3: e.g. a sub-cell array comprising MCELL C00-C30 coupled to bit lines BL0-BLN0 and supply line 340); and
a respective assist circuit connected to the respective sub-cell array through a respective supply line (FIG. 3: power switch PSW 308), and configured to pre-charge the respective supply line with a supply voltage during a stand-by mode (FIGS. 9 and 6c: maintain supply line 340 at VDDL during RETAIN with PSZ inactive high)
Deng teaches the respective assist circuit is in response to respective column select signal CS[3:0] generated by column decoder 116 (see FIGS. 3 and 5) instead of row select signal WL generated by row decoder 114.
Akamatsu teaches a memory cell connected to an assist circuit through a supply line (FIGS. 6-7: latch cell 52A coupled to an assist circuit 144A through dynamic voltage line VPERIZn); the assist circuit configured to block the supply line upon initiation of a write operation based on row select signal WL (see 7:50-65 and 8:15-57).
Since Deng and Akamatsu are both from the same field of endeavor, the purpose disclosed by Akamatsu would have been recognized in the pertinent art of Deng.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace column select signal CS of Deng with row select signal WL of Akamatsu in order to increasing the write assist power by blocking the supply line upon initiation of a write operation (see 8:41-47). With the proposed modification, a person with ordinary skill in the art can simply replace column select signals CS[3:0] with corresponding row select signal WL in FIG. 5 of Deng.
Regarding dependent claim 14, Deng teaches wherein the column peripheral circuit includes: a plurality of column decoders configured to select a plurality of column select lines connected to the memory cell array based on first address information (FIG. 1a: column select lines are outputs of column decoder 116 in response to column address); and a plurality of control logic circuits (see FIG. 5) configured to control the assist circuit based on a control signal (see FIG. 3).
Regarding dependent claim 15, Deng teaches wherein each of the plurality of control logic circuits is configured to simultaneously control two assist circuits among a plurality of assist circuits corresponding to the plurality of unit cell circuits (FIG. 3: e.g. control logic generating signal PSZ[0] for controlling PSW 308 and PSW 316).
Regarding dependent claim 16, Deng teaches wherein each of the plurality of control logic circuits is configured to generate its control signal based on second address information (FIG. 1a: because column address is based on row and column address 144), a write clock signal (FIG. 5: signal W), and a retention signal (FIG. 5: combination of signals W and R).
Regarding dependent claim 17, Deng teaches wherein the retention signal is defined such that the control signal corresponds to a logic high value in a retention mode (FIGS. 6c and 9: signal PSZ inactive high puts the assist circuit in retention mode).
Regarding dependent claim 18, Deng teaches a memory column circuit comprising:
a control logic circuit configured to provide a control signal (FIG. 5: logic circuit providing signal PSZ[0]); and
a unit cell circuit comprising:
an assist circuit configured to receive the control signal (FIG. 3: power switch PSW 308 receiving signal PSZ[0]), pre-charge a supply line with a supply voltage during a stand-by mode based on the control signal (FIGS. 9 and 6c: maintain supply line 340 at VDDL during RETAIN with PSZ inactive high)
a sub-cell array including a plurality of memory cells each connected to the supply line (FIG. 3: e.g. a sub-cell array comprising MCELL C00-C30 coupled to bit lines BL0-BLN0 and supply line 340).
Deng teaches the respective assist circuit is in response to respective column select signal CS[3:0] generated by column decoder 116 (see FIGS. 3 and 5) instead of row select signal WL generated by row decoder 114.
Akamatsu teaches a memory cell connected to an assist circuit through a supply line (FIGS. 6-7: latch cell 52A coupled to an assist circuit 144A through dynamic voltage line VPERIZn); the assist circuit configured to block the supply line upon initiation of a write operation based on row select signal WL (see 7:50-65 and 8:15-57).
Since Deng and Akamatsu are both from the same field of endeavor, the purpose disclosed by Akamatsu would have been recognized in the pertinent art of Deng.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace column select signal CS of Deng with row select signal WL of Akamatsu in order to increasing the write assist power by blocking the supply line upon initiation of a write operation (see 8:41-47). With the proposed modification, a person with ordinary skill in the art can simply replace column select signals CS[3:0] with corresponding row select signal WL in FIG. 5 of Deng.
Regarding dependent claim 19, Deng teaches wherein the control logic circuit generates the control signal based on address information (FIG. 1a: column select lines are outputs of column decoder 116 in response to column address), a write clock signal (FIG. 5: signal W), and a retention signal for a retention mode (FIG. 5: combination of signals W and R).
Regarding dependent claim 20, Deng teaches wherein the control signal is generated to cause the assist circuit to block the supply line when the retention mode initiates (FIGS. 9 and 6c: VNND is blocked, VDDL is supplied to power line 340 instead).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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June 3, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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