DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
I. INFORMATION DISCLOSURE STATEMENT
The information disclosure statement (IDS) submitted on 10/14/2024 and 01/07/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
II. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over O’Brien et al. (US Patent 8,296,526) in view of Furukawa et al. (US Pub.: 2009/0287850).
As per claim 1, O’Brien teaches/suggests a method, comprising:
first operating based on first instructions from a processor and second based on second instructions from the processor, the first indicative of a first quantity of data banks to access for first data, the second indicative of a second quantity of data banks to access for second data (e.g. associated with first memory access instruction and second memory access instruction from the processor for accessing memory bank in memory device: Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42);
locating the first data for a first data access operation in a first data bank of at least one of a store queue or a storage (e.g. associated location at memory device (108) would need to be located when the processor accesses corresponding memory bank for first read/write operation: Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42);
locating the second data for a second data access operation in a second data bank of at least one of the store queue or the storage (e.g. associated location at memory device (108) would need to be located when the processor accesses corresponding memory bank for second read/write operation: Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42).
O’Brien does not teach the method, comprising:
generating first transaction data and second transaction data, the first transaction data indicative of a first operation, the second transaction data indicative of a second operation;
based on the first data bank being different from the second data bank, assigning the first transaction data to be transmitted to the first data bank and the second transaction data to be transmitted to the second data bank.
Furukawa teaches/suggests a method, comprising: generating first transaction data and second transaction data , the first transaction data indicative of a first operation, the second transaction data indicative of a second operation (e.g. associated with generating first subcommand group and second subcommand group: [0085]-[0086]); based on the first data bank being different from the second data bank (e.g. associated with determining whether or not the commands access different banks (Step S103) of Fig. 6; Fig. 6, [0133]), assigning the first transaction data to be transmitted to the first data bank and the second transaction data to be transmitted to the second data bank (e.g. associated forwarding corresponding command for accessing first bank (Step S104) and forwarding corresponding command for accessing second bank (Step S105) in Fig. 6: Fig. 6; [0134]-[0137]) (Fig. 6; [0081]-[0090]; and [0130]-[0142]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Furukawa’s subcommand groups into O’Brien’s memory accessing operations for the benefit of improving access efficiency while lowering power consumption (Furukawa, [0023]-[0024]) to obtain the invention as specified in claim 1.
As per claim 2, O’Brien and Furukawa teach/suggest all the claimed features of claim 1 above, where O’Brien and Furukawa further teach/suggest the method further comprising: based on the first data bank being the same as the second data bank, determining whether the first data access operation or the second data access operation is a read data operation or a write data operation; and based on the first data access operation being the read data operation and the second data access operation being a write data operation, assigning the first transaction data to be transmitted to the first data bank and not assigning the second transaction data to be transmitted (O’Brien, Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42; and Furukawa, Fig. 6; [0081]-[0090]; [0130]-[0142]), wherein it would have been obvious that the resulting combination of the references would further teach/suggest the above claimed features as reading and writing of memory banks are properly carried out.
As per claim 3, O’Brien and Furukawa teach/suggest all the claimed features of claim 1 above, where O’Brien and Furukawa further teach/suggest the method comprising: wherein the first data access operation includes reading a first portion of the first data from one or more of the first data banks and writing a second portion of the first data to one or more of the second data banks, the first data bank included in the one or more of the first data banks or the one or more of the second data banks, and wherein the method further comprises: based on locating the first portion in the first data banks of the store queue: transmitting the first portion from the store queue to the storage; transmitting a control signal from the store queue to arbiter logic, the arbiter logic coupled to the storage; and based on the arbiter logic obtaining the control signal, writing the first portion and the second portion to the storage (O’Brien, Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42; and Furukawa, Fig. 6; [0081]-[0090]; [0130]-[0142]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as reading and writing of memory banks are properly carried out.
As per claim 4, O’Brien and Furukawa teach/suggest all the claimed features of claim 1 above, where O’Brien and Furukawa further teach/suggest the method comprising: wherein the first data bank is included in the store queue, and wherein the method further comprises, based on the store queue being full, instructing arbiter logic coupled to the store queue to prevent assigning the first transaction data to be transmitted to the first data bank (O’Brien, Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42; and Furukawa, Fig. 6; [0081]-[0090]; [0130]-[0142]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as reading and writing of memory banks are properly carried out.
As per claim 5, O’Brien and Furukawa teach/suggest all the claimed features of claim 1 above, where O’Brien and Furukawa further teach/suggest the method further comprising: determining a data access operation data size based on the first instructions; determining a data storage address based on the first instructions; mapping the data access operation data size and the data storage address to the first quantity of data banks to be accessed, the first quantity of data banks including a first data bank and a second data bank; and determining that the data access operation includes reading a first portion of the first data from the first data bank and writing a second portion of the first data to the second data bank (O’Brien, Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42; and Furukawa, Fig. 6; [0081]-[0090]; [0130]-[0142]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as reading and writing of memory banks are properly carried out.
As per claim 6, O’Brien and Furukawa teach/suggest all the claimed features of claim 1 above, where O’Brien and Furukawa further teach/suggest the method further comprising: transmitting the first transaction data to the first data bank and the second transaction data to the second data bank in parallel (O’Brien, Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42; and Furukawa, Fig. 6; [0081]-[0090]; [0130]-[0142]).
As per claim 7, O’Brien and Furukawa teach/suggest all the claimed features of claim 6 above, where O’Brien and Furukawa further teach/suggest the method comprising: wherein transmitting the first transaction data to the first data bank and the second transaction data to the second data bank in parallel comprises transmitting the first transaction data to the first data bank and the second transaction data to the second data bank in a same clock cycle (O’Brien, Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42; and Furukawa, Fig. 6; [0081]-[0090]; [0130]-[0142]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as reading and writing of memory banks are properly carried out.
As per claim 8, O’Brien and Furukawa teach/suggest all the claimed features of claim 1 above, where O’Brien and Furukawa further teach/suggest the method comprising: wherein the storage and the store queue each includes a set of data banks, and wherein each one of the set of data banks of the storage corresponds to a respective one of the set of data banks of the store queue (O’Brien, Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42; and Furukawa, Fig. 6; [0081]-[0090]; [0130]-[0142]; [0190]; [0195]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as reading and writing of memory banks are properly carried out.
As per claim 9, O’Brien and Furukawa teach/suggest all the claimed features of claim 8 above, where O’Brien and Furukawa further teach/suggest the method comprising: wherein the set of data banks of the storage includes 16 data banks, and wherein the set of data banks of the store queue includes 16 data banks (O’Brien, Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42; and Furukawa, Fig. 6; [0081]-[0090]; [0130]-[0142]), wherein it would have been obvious design choice to one of ordinary skilled in the art to further implement the above claimed features for reading and writing operations.
As per claim 10, O’Brien and Furukawa teach/suggest all the claimed features of claim 1 above, where O’Brien and Furukawa further teach/suggest the method comprising: wherein the storage is a level-one (L1) main cache storage and the store queue is an L1 main cache store queue, or the storage is an L1 victim cache storage and the store queue is an L1 victim cache store queue (O’Brien, Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42; and Furukawa, Fig. 6; [0081]-[0090]; [0130]-[0142]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as reading and writing of memory banks are properly carried out.
As per claims 11, claim 11 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1, where O’Brien and Furukawa further teach/suggest the system comprising: a cache storage; a cache store queue coupled to the cache storage; and a cache controller coupled to the cache storage and the cache store queue and configured to operate accordingly (O’Brien, Fig. 1-2; col. 5, l. 31 to col. 6, l. 7; col. 10, ll. 33-42; and Furukawa, Fig. 6; [0081]-[0090]; [0130]-[0142]; [0190]; [0195]).
As per claims 12-20, claims 12-20 are rejected in accordance to the same rational and reasoning as the above rejection of claims 2-10.
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 March 07, 2026