Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Oath/Declaration
Oath/Declaration as file 10/14/2024 is noted by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “…a first measurement circuit disposed in the first region proximate to the first electrical component…” in lines 3-4 of Claim 1. It is not clear if the underlined limitation in question refers to the same “first region of the substrate” disclosed earlier in Claim 1 or if it refers to a different “first region”. If this is the case, then please change the limitation in question to “the first region of the substrate”.
Claim 1 recites the limitation “…a second measurement circuit disposed in the second region proximate to the second electrical component…” in lines 7-8 of Claim 1. It is not clear if the underlined limitation in question refers to the same “second region of the substrate” disclosed earlier in Claim 1 or if it refers to a different “second region”. If this is the case, then please change the limitation in question to “the second region of the substrate”.
Claim 1 recites the limitation “…a stress induction device disposed on the substrate above the second region.” in line 9 of Claim 1. It is not clear if the underlined limitation in question refers to the same “second region of the substrate” disclosed earlier in Claim 1 or if it refers to a different “second region”. If this is the case, then please change the limitation in question to “the second region of the substrate”.
Claim 4 recites the limitation “…wherein the stress induction device is not above the first region.” in lines 1-3 of Claim 4. It is not clear if the underlined limitation in question refers to the same “first region of the substrate” disclosed earlier in Claim 1 or if it refers to a different “first region”. If this is the case, then please change the limitation in question to “the first region of the substrate”.
Claim 6 recites the limitation “…a third measurement circuit disposed in the third region proximate to the third electrical component…” in lines 3-4 of Claim 6. It is not clear if the underlined limitation in question refers to the same “third region of the substrate” disclosed earlier in Claim 6 or if it refers to a different “third region”. If this is the case, then please change the limitation in question to “the third region of the substrate”.
Claim 6 recites the limitation “…; a fourth measurement circuit disposed in the fourth region proximate to the first electrical component; and a second stress induction device disposed on the substrate above the fourth region …” in lines 7-10 of Claim 6. It is not clear if the underlined limitation in question refers to the same “fourth region of the substrate” disclosed earlier in Claim 6 or if it refers to a different “fourth region”. If this is the case, then please change the limitation in question to “the fourth region of the substrate”.
Claim 8 recites the limitation “…wherein the first region is under mechanical stress applied to the first region…” in lines 2-3 of Claim 8. It is not clear if the underlined limitation in question refers to the same “first region of the substrate” disclosed earlier in Claim 8 or if it refers to a different “first region”. If this is the case, then please change the limitation in question to “the first region of the substrate”.
Claim 8 recites the limitation “…the second region of the substrate proximate to the first region of the substrate but outside of the first region…” in lines 3-5 of Claim 8. It is not clear if the underlined limitation in question refers to the same “first region of the substrate” disclosed earlier in Claim 8 or if it refers to a different “first region”. If this is the case, then please change the limitation in question to “the first region of the substrate”.
Claim 16 recites the limitation “…disposing a second electrical component in a second region of the substrate proximate to the first region…” in lines 3-4 of Claim 16. It is not clear if the underlined limitation in question refers to the same “first region of the substrate” disclosed earlier in Claim 16 or if it refers to a different “first region”. If this is the case, then please change the limitation in question to “the first region of the substrate”.
Claim 16 recites the limitation “…disposing a stress induction device on the substrate above the first region…” in line 7 of Claim 16. It is not clear if the underlined limitation in question refers to the same “first region of the substrate” disclosed earlier in Claim 16 or if it refers to a different “first region”. If this is the case, then please change the limitation in question to “the first region of the substrate”.
Claims 2-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as they further limit Claim 1.
Claims 9-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as they further limit Claim 8.
Claims 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as they further limit Claim 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 8, 9, 16, 17, 19 and 20 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Ausserlechner US 2024/0110839 (Hereinafter Ausserlechner).
Regarding claim 1, Ausserlechner teaches a circuit (Figs. 1, 6), comprising:
a first electrical component (Fig. 1; stress sensitive elements, 121, 122) disposed in a first region (Fig. 1; first region, 120) of a substrate (Fig. 1; substrate, 110);
a first measurement circuit (Fig. 1; measuring circuit, 140; sensor element, 160) disposed in the first region (Fig. 1; first region, 120) proximate to the first electrical component (Fig. 1; stress sensitive elements, 121, 122);
a second electrical component (Fig. 1; stress sensitive elements, 131, 132) disposed in a second region (Fig. 1; second region, 130) of the substrate (Fig. 1; substrate, 110), the second region of the substrate proximate to the first region (Fig. 1; first region, 120) of the substrate (Fig. 1; substrate, 110);
a second measurement circuit (Fig. 1; 140, 150) disposed in the second region (Fig. 1; second region, 130) proximate to the second electrical component (Fig. 1; stress sensitive elements, 131, 132); and
a stress induction device (Figs. 1-3; [0023-0024, 0043, 0051]; stress tensor) disposed on the substrate (Fig. 1; substrate, 110) above the second region (Fig. 1; stress sensitive elements, 131, 132).
Regarding claim 2, Ausserlechner further teaches the circuit of claim 1, wherein the stress induction device includes a bond pad and a plurality of vias (Figs. 1-3; [0023-0024, 0035-0038, 0043, 0051]; stress tensor).
Regarding claim 3, Ausserlechner further teaches the circuit of claim 2, wherein the stress induction device includes a bond wire coupled to the bond pad (Figs. 1-3; [0023-0024, 0035-0038, 0043, 0051]; stress tensor).
Regarding claim 4, Ausserlechner further teaches the circuit of claim 1, wherein the stress induction device is not above the first region (Figs. 1-3; [0023-0024, 0035-0038, 0043, 0051]; stress tensor).
Regarding claim 5, Ausserlechner further teaches the circuit of claim 1, wherein the second electrical component (Fig. 1; stress sensitive elements, 131, 132) has characteristics within a threshold variance of the first electrical component (Fig. 1; stress sensitive elements, 121, 122), and wherein the second measurement circuit (Fig. 1; 140, 150) has characteristics within a threshold variance of the first measurement circuit (Fig. 1; measuring circuit, 140; sensor element, 160).
Regarding claim 8, Ausserlechner teaches a circuit (Figs. 1, 6), comprising:
a first electrical component (Fig. 1; stress sensitive elements, 121, 122) disposed in a first region (Fig. 1; first region, 120) of a substrate (Fig. 1; substrate, 110), wherein the first region (Fig. 1; first region, 120) is under mechanical stress (Figs. 1-3; [0023-0024, 0043, 0051]; stress tensor) applied to the first region (Fig. 1; first region, 120);
a second electrical component (Fig. 1; stress sensitive elements, 131, 132) disposed in a second region (Fig. 1; second region, 130) of the substrate (Fig. 1; substrate, 110), the second region (Fig. 1; second region, 130) of the substrate (Fig. 1; substrate, 110) proximate to the first region (Fig. 1; first region, 120) of the substrate (Fig. 1; substrate, 110) but outside of the first region (Fig. 1; first region, 120); and
a measurement circuit (Fig. 1; measuring circuit, 140) coupled to the first electrical component (Fig. 1; stress sensitive elements, 121, 122) and the second electrical component (Fig. 1; stress sensitive elements, 131, 132).
Regarding claim 9, Ausserlechner further teaches the circuit of claim 8, wherein the first electrical component (Fig. 1; stress sensitive elements, 121, 122) and the second electrical component (Fig. 1; stress sensitive elements, 131, 132) are each semiconductor devices (Fig. 1; 121, 122, 131, 132).
Regarding claim 16, Ausserlechner teaches a method (Figs. 1, 6), comprising:
disposing a first electrical component (Fig. 1; stress sensitive elements, 121, 122) in a first region (Fig. 1; first region, 120) of a substrate (Fig. 1; substrate, 110);
disposing a second electrical component (Fig. 1; stress sensitive elements, 131, 132) in a second region (Fig. 1; second region, 130) of the substrate (Fig. 1; substrate, 110) proximate to the first region (Fig. 1; first region, 120);
disposing a measurement circuit (Fig. 1; measuring circuit, 140) coupled to at least one of the first electrical component (Fig. 1; stress sensitive elements, 121, 122) or the second electrical component (Fig. 1; stress sensitive elements, 131, 132); and
disposing a stress induction device (Figs. 1-3; [0023-0024, 0043, 0051]; stress tensor) on the substrate (Fig. 1; substrate, 110) above the first region (Fig. 1; first region, 120).
Regarding claim 17, Ausserlechner further teaches the method of claim 16, wherein the measurement circuit is a first measurement circuit (Fig. 1; measuring circuit, 140; sensor element, 160) disposed proximate to the first electrical component (Fig. 1; stress sensitive elements, 121, 122) and coupled to the first electrical component (Fig. 1; stress sensitive elements, 121, 122), the method further comprising: disposing a second measurement circuit (Fig. 1; 140, 150) proximate to the second electrical component (Fig. 1; stress sensitive elements, 131, 132), the second measurement circuit (Fig. 1; 140, 150) coupled to the second electrical component (Fig. 1; stress sensitive elements, 131, 132).
Regarding claim 19, Ausserlechner further teaches the method of claim 16, wherein the first (Fig. 1; stress sensitive elements, 121, 122) and second electrical components (Fig. 1; stress sensitive elements, 131, 132) are each semiconductor devices (Fig. 1; 121, 122, 131, 132).
Regarding claim 20, Ausserlechner further teaches the method of claim 16, wherein the stress induction device includes one or more of a bond wire, a bond pad, a via, or metallization (Figs. 1-3; [0023-0024, 0035-0038, 0043, 0051]; stress tensor).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ausserlechner in view of Kishore Kumar et al. US 2024/0230815 (Hereinafter Kishore Kumar).
Regarding claim 14, Ausserlechner teaches the circuit of claim 8, but not specifically further comprising a trim circuit coupled to the measurement circuit, the first electrical component, and the second electrical component.
However, Kishore Kumar does teach a trim circuit (Figs. 1, 2; trim controller, 250) coupled to the measurement circuit, the first electrical component, and the second electrical component (Figs. 1, 2; trim controller, 250).
It would have been obvious before the effective filing date of the claimed invention to modify the semiconductor circuit arrangement of Ausserlechner by implementing the teachings of Kishore Kumar regarding a trim circuit coupled to the measurement circuit, the first electrical component, and the second electrical component; in order to “obtain first sense signals responsive to a test voltage applied to the sense resistor by the test circuit, the test voltage being a direct-circuit voltage; and obtain second sense signals responsive a supply voltage applied to the sense resistor by the driver circuit” (See Kishore Kumar; Abstract).
Regarding claim 18, Ausserlechner teaches the method of claim 16, but not specifically further comprising: disposing a trim circuit on the substrate, the trim circuit coupled to the measurement circuit; determining an effect of stress on the first electrical component based on a comparison of output signals of the first and second electrical components; determining a stress compensation for the first electrical component; and applying, via the trim circuit, the stress compensation to the first electrical component.
However, Kishore Kumar does teach disposing a trim circuit on the substrate, the trim circuit coupled to the measurement circuit (Figs. 1, 2; trim controller, 250); determining an effect of stress on the first electrical component based on a comparison of output signals of the first and second electrical components (Figs. 1, 2; trim controller, 250); determining a stress compensation for the first electrical component (Figs. 1, 2; trim controller, 250); and applying, via the trim circuit, the stress compensation to the first electrical component (Figs. 1, 2; trim controller, 250).
It would have been obvious before the effective filing date of the claimed invention to modify the semiconductor circuit arrangement of Ausserlechner by implementing the teachings of Kishore Kumar regarding disposing a trim circuit on the substrate, the trim circuit coupled to the measurement circuit; determining an effect of stress on the first electrical component based on a comparison of output signals of the first and second electrical components; determining a stress compensation for the first electrical component; and applying, via the trim circuit, the stress compensation to the first electrical component; in order to “obtain first sense signals responsive to a test voltage applied to the sense resistor by the test circuit, the test voltage being a direct-circuit voltage; and obtain second sense signals responsive a supply voltage applied to the sense resistor by the driver circuit” (See Kishore Kumar; Abstract).
Allowable Subject Matter
Claims 6, 7, 10-13 and 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 6, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 1,
“…a third electrical component disposed in a third region of the substrate; a third measurement circuit disposed in the third region proximate to the third electrical component; a fourth electrical component disposed in a fourth region of the substrate, the fourth region of the substrate proximate to the third region of the substrate; a fourth measurement circuit disposed in the fourth region proximate to the first electrical component; and a second stress induction device disposed on the substrate above the fourth region, wherein the first and second regions of the substrate are in a first stress zone, and the third and fourth regions of the substrate are in a second stress zone separate from the first stress zone.”
Claim 7 is also allowed as it further limits objected claim 6.
Regarding claim 10, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 8,
“…wherein further comprising a variable resistor having first and second terminals, a resistor having first and second terminals, a current source having first and second terminals, and an amplifier having first and second inputs and having first and second output terminals, wherein the measurement circuit includes a differential amplifier, the first electrical component has a first terminal coupled to a ground terminal of the circuit and a second terminal coupled to the first terminal of the variable resistor, the second terminal of the variable resistor is coupled to a first input terminal of the differential amplifier, the first terminal of the current source is coupled to a voltage supply terminal and the second terminal of the current source is coupled to the first input terminal of the differential amplifier, the second electrical component has a first terminal coupled to the ground terminal of the circuit and a second terminal coupled to the first terminal of the resistor, the second terminal of the resistor is coupled to a second input terminal of the differential amplifier, the first input terminal of the amplifier coupled to the output terminal of the differential amplifier, the second input terminal of the amplifier coupled to the voltage supply terminal, and the first output terminal of the amplifier coupled to the second input terminal of the differential amplifier.”
Claim 11 is also allowed as it further limits objected claim 10.
Regarding claim 12, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 8,
“…wherein the measurement circuit comprises: a first switch having first and second terminals, the first terminal of the first switch coupled to a first terminal of the first electrical component and the second terminal of the first switch coupled to a second terminal of the first electrical component, wherein a second terminal of the first electrical component is coupled to a ground terminal; a second switch having first and second terminals, the first terminal of the second switch coupled to a first terminal of the second electrical component and the second terminal of the second switch coupled to a second terminal of the second electrical component, wherein a second terminal of the second electrical component is coupled to the ground terminal; a resistor; having first and second terminals, the second terminal of the resistor coupled to the first terminal of the second electrical component; a first transistor having a control terminal and first and second terminals, the first terminal of the first transistor coupled to the control terminal of the first transistor, and the second terminal of the first transistor coupled to the first terminal of the first electrical component; a second transistor having a control terminal and first and second terminals, the control terminal of the second transistor coupled to the control terminal of the first transistor, and the second terminal of the second transistor coupled to the first terminal of the resistor; a third transistor having a control terminal and first and second terminals, the control terminal of the third transistor coupled to the first terminal of the second transistor, and the first terminal of the third transistor coupled to the control terminal of the first transistor; a fourth transistor having a control terminal and first and second terminals, the control terminal of the fourth transistor coupled to the control terminal of the third transistor, the first terminal of the fourth transistor coupled to the first terminal of the second transistor, and the second terminal of the fourth transistor coupled to the second terminal of the third transistor; and a fifth transistor having a control terminal and first and second terminals, the control terminal of the fifth transistor coupled to the control terminal of the fourth transistor, and the second terminal of the fifth transistor coupled to the second terminal of the fourth transistor.”
Claim 13 is also allowed as it further limits objected claim 12.
Regarding claim 15, the prior art does not teach or suggest, in combination with the rest of the limitations of claims 8 and 14,
“…a current source having first and second terminals; a first switch having first and second terminals, the second terminal of the first switch coupled to the second terminal of the current source; and a second switch having first and second terminals, the first terminal of the second switch coupled to the second terminal of the current source, wherein the first electrical component is a first resistor having first and second terminals, the first terminal of the first resistor coupled to the first terminal of the first switch, and the second terminal of the first resistor coupled to a ground terminal, and wherein the second electrical component is a second resistor having first and second terminals, the first terminal of the second resistor coupled to the second terminal of the second switch, and the second terminal of the second resistor coupled to the ground terminal.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Theuss et al. US 2013/0175527 - A sensor arrangement is provided, the sensor arrangement including a chip including a sensor circuit configured to detect a bending of the chip; and a package structure configured to protect the chip; wherein the package structure includes a first region and a second region, and wherein the package structure is configured such that it is easier to be deformed in the first region than in the second region.
Zhang et al. US 2014/0191777 - A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor. Each of the multiplexers has an input coupled to one of the monitor nodes and a respective node of the amplifier circuit. In operation, the multiplexers selectively insert the degradation test transistor into either the integrated circuit or the amplifier circuit so that when inserted into the integrated circuit the degradation test transistor is subjected to stress degradation voltages in the integrated circuit.
Li et al. US 2015/0155245 - A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical component. The arrangement also includes a monitoring layer configured to evaluate electrical performance of the electrical component.
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/RAUL J RIOS RUSSO/Examiner, Art Unit 2858
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