Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending in this action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/15/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-16, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodeheffer et al (US 2003/0,097,608), in view of Luck (US 2018/0,190,365)
As per claim 1:
Rodeheffer discloses:
A device comprising:
(Rodeheffer, Figs 1-6)
a plurality of memory blocks; a plurality of connections respectively coupled to the plurality of memory blocks; and control logic coupled to the plurality of memory blocks, the control logic configurable to control performance of error-related transactions on the plurality of memory blocks via the plurality of connections, including to:
(Rodeheffer, [0034], system 10 includes a memory 12 that is divided into several memory modules 14 that are each coupled to a memory bus 50. Each memory module 14 includes a memory subcontroller 16 and a memory array 18. Memory array 18 is typically random access memory (RAM). Each subcontroller 16 has the responsibility for scanning its own RAM 18 to detect corrupt bits and to perform this task independently of the other subcontrollers 16. System 10 includes a central processing unit (CPU) 20 that includes a processor core 22, and an optional hierarchy of N levels of cache memory 24-1 to 24-N)
cause a first error-related transaction to be performed on a first memory block of the plurality of memory blocks during a first time period,
(Rodeheffer, Fig. 6, 202-N-M, 206-N-M)
(Rodeheffer, Fig. 6, Access Controller 612, Error Detection/Correction 614, and ECC Encoder 616 are coupled to memories 202-N-M, 206-N-M)
cause a second error-related transaction to be performed on a second memory block of the plurality of memory blocks during a second time period, and
(Rodeheffer, Fig. 6, 202-N-M, 206-N-M)
(Rodeheffer, Fig. 6, Access Controller 612, Error Detection/Correction 614, and ECC Encoder 616 are coupled to memories 202-N-M, 206-N-M)
cause a transaction that is not an error-related transaction to be performed on at least one of the plurality of memory blocks,
(Rodeheffer, Fig. 6, 202-N-M, 206-N-M)
(Rodeheffer, Fig. 6, Access Controller 612, Error Detection/Correction 614, and ECC Encoder 616 are coupled to memories 202-N-M, 206-N-M)
(Rodeheffer, [0034] Each subcontroller 16 has the responsibility for scanning its own RAM 18 to detect corrupt bits and to perform this task independently of the other subcontrollers 16)
(Rodeheffer, [0034] Each subcontroller 16 has the responsibility for scanning its own RAM 18 to detect corrupt bits and to perform this task independently of the other subcontrollers 16)
Rodeheffer does not clearly disclose:
cause a transaction …except the first memory block
Luck discloses:
cause a transaction …except the first memory block
(Luck, [0045], computing system 100 may include multiple memory controllers that may scrub different blocks of memory simultaneous or in parallel… may perform memory scrubbing operations independent of each other)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Luck’s multiple controllers with scrubber in order to allow the system freedom to scrub different blocks of memory simultaneous or in parallel or independent of each other.
(Luck, [0045], … multiple memory controllers that may scrub different blocks of memory simultaneous or in parallel… may perform memory scrubbing operations independent of each other)
As per claim 2:
Rodeheffer-Luck further discloses:
wherein the first time period and the second time period at least partially overlap.
(Rodehefferr, [0024] the scan rate is effectively increased by moving the scrubbing function into the memory system and distributing it among a number of subcomponents that operate in parallel)
(Rodeheffer, [0034] Each subcontroller 16 has the responsibility for scanning its own RAM 18 to detect corrupt bits and to perform this task independently of the other subcontrollers 16)
As per claim 3:
Rodeheffer-Luck further discloses:
wherein the first time period and the second time period do not overlap.
(Rodeheffer, [0039]… An important advantage of the present invention is that the memory scrubbing schedule used by scan scheduler 210 is not dependent upon the schedule used by other memory modules 14 in memory 12 (FIG. 1))
(Rodeheffer, [0034] Each subcontroller 16 has the responsibility for scanning its own RAM 18 to detect corrupt bits and to perform this task independently of the other subcontrollers 16)
As per claim 4:
Rodeheffer-Luck further discloses:
a controller coupled to each of the plurality of memory blocks, wherein the control logic is disposed in the controller.
(Rodeheffer, [0034] Each subcontroller 16 has the responsibility for scanning its own RAM 18 to detect corrupt bits and to perform this task independently of the other subcontrollers 16)
As per claim 5:
Rodeheffer-Luck further discloses:
wherein each of the plurality of connections includes a pipeline circuit, and the control logic includes instances of control logic, in which a corresponding instance of control logic is disposed in a respective pipeline circuit.
(Rodeheffer, [0034], system 10 includes a memory 12 that is divided into several memory modules 14 that are each coupled to a memory bus 50. Each memory module 14 includes a memory subcontroller 16 and a memory array 18. Memory array 18 is typically random access memory (RAM). Each subcontroller 16 has the responsibility for scanning its own RAM 18 to detect corrupt bits and to perform this task independently of the other subcontrollers 16. System 10 includes a central processing unit (CPU) 20 that includes a processor core 22, and an optional hierarchy of N levels of cache memory 24-1 to 24-N)
(Rodeheffer, [0025] advantage of memory systems in accordance with this embodiment is that the scan rate is effectively increased, since each memory module in the memory system may concurrently perform memory scrubbing in accordance with the memory scrubbing schedule)
(Rodeheffer, [0039]… An important advantage of the present invention is that the memory scrubbing schedule used by scan scheduler 210 is not dependent upon the schedule used by other memory modules 14 in memory 12 (FIG. 1))
As per claim 6:
Rodeheffer-Luck further discloses:
wherein each of the first and second error-related transactions includes an error correcting code (ECC) scrubbing transaction.
(Rodeheffer, Fig. 3 ECC code 1-N)
As per claim 9:
Rodeheffer-Luck further discloses:
a level-two (L2) cache SRAM that includes the first memory block and the second memory block; and an L2 cache controller that includes the control logic.
(Rodeheffer, [0034],.. Each memory module 14 includes a memory subcontroller 16 and a memory array 18. Memory array 18 is typically random access memory (RAM). Each subcontroller 16 has the responsibility for scanning its own RAM 18 to detect corrupt bits and to perform this task independently of the other subcontrollers 16. System 10 includes a central processing unit (CPU) 20 that includes a processor core 22, and an optional hierarchy of N levels of cache memory 24-1 to 24-N)
(Rodeheffer, [0029] FIG. 2 … memory module that includes memory controller logic and ECC RAM memory …)
As per claim 10:
Rodeheffer-Luck further discloses:
a processor core coupled to the L2 cache SRAM.
(Rodeheffer, [0034…System 10 includes a central processing unit (CPU) 20 that includes a processor core 22, and an optional hierarchy of N levels of cache memory 24-1 to 24-N)
(Rodeheffer, [0029] FIG. 2 … memory module that includes memory controller logic and ECC RAM memory …)
As per claim 11:
Rodeheffer-Luck further discloses:
wherein the control logic is configurable to set the plurality of connections in a test mode in which all error-related transactions performed on the plurality of memory blocks are performed in the test mode.
(Rodeheffer [0039] access controller 212 also initiates a remedial action when a normal memory access operation (as opposed to a scrubbing scan operation) results in detection of an error by the error detection logic 214… send a request to another device, such as the main memory controller 40 or the CPU 20 to generate a corrected memory line using the ECC code for the memory line (or for the portion of the memory line determined to have been corrupted) and to write the corrected memory line back to memory 18)
As per claim 12:
Rodeheffer discloses:
A method comprising:
(Rodeheffer, [0034], system 10 includes a memory 12 that is divided into several memory modules 14 that are each coupled to a memory bus 50. Each memory module 14 includes a memory subcontroller 16 and a memory array 18. Memory array 18 is typically random access memory (RAM). Each subcontroller 16 has the responsibility for scanning its own RAM 18 to detect corrupt bits and to perform this task independently of the other subcontrollers 16. System 10 includes a central processing unit (CPU) 20 that includes a processor core 22, and an optional hierarchy of N levels of cache memory 24-1 to 24-N)
receiving error-related transaction values; and
Rodeheffer, [0034], system 10 includes a memory 12 that is divided into several memory modules 14 that are each coupled to a memory bus 50. Each memory module 14 includes a memory subcontroller 16 and a memory array 18. Memory array 18 is typically random access memory (RAM). Each subcontroller 16 has the responsibility for scanning its own RAM 18 to detect corrupt bits and to perform this task independently of the other subcontrollers 16. System 10 includes a central processing unit (CPU) 20 that includes a processor core 22, and an optional hierarchy of N levels of cache memory 24-1 to 24-N)
(Rodeheffer, [0025] advantage of memory systems in accordance with this embodiment is that the scan rate is effectively increased, since each memory module in the memory system may concurrently perform memory scrubbing in accordance with the memory scrubbing schedule)
(Rodeheffer, [0039]… An important advantage of the present invention is that the memory scrubbing schedule used by scan scheduler 210 is not dependent upon the schedule used by other memory modules 14 in memory 12 (FIG. 1))
based on the error-related transaction values: performing a first error-related transaction on a first memory block during a first time period;
(Rodeheffer [0039] access controller 212 also initiates a remedial action when a normal memory access operation (as opposed to a scrubbing scan operation) results in detection of an error by the error detection logic 214… send a request to another device, such as the main memory controller 40 or the CPU 20 to generate a corrected memory line using the ECC code for the memory line (or for the portion of the memory line determined to have been corrupted) and to write the corrected memory line back to memory 18)
performing a second error-related transaction on a second memory block during a second time period that at least partially overlaps the first time period; and
(Rodeheffer [0039] access controller 212 also initiates a remedial action when a normal memory access operation (as opposed to a scrubbing scan operation) results in detection of an error by the error detection logic 214… send a request to another device, such as the main memory controller 40 or the CPU 20 to generate a corrected memory line using the ECC code for the memory line (or for the portion of the memory line determined to have been corrupted) and to write the corrected memory line back to memory 18)
performing a transaction that is not an error-related transaction on the second memory block
(Rodeheffer, [0025] advantage of memory systems in accordance with this embodiment is that the scan rate is effectively increased, since each memory module in the memory system may concurrently perform memory scrubbing in accordance with the memory scrubbing schedule)
Rodeheffer does not clearly disclose:
performing a transaction …during a third time period that at least partially overlaps with the first time period, the second and third time periods being mutually exclusive.
Luck discloses:
performing a transaction …during a third time period that at least partially overlaps with the first time period, the second and third time periods being mutually exclusive.
(Luck, [0045], computing system 100 may include multiple memory controllers that may scrub different blocks of memory simultaneous or in parallel… may perform memory scrubbing operations independent of each other)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Luck’s multiple controllers with scrubber in order to allow the system freedom to scrub different blocks of memory simultaneous or in parallel or independent of each other.
(Luck, [0045], … multiple memory controllers that may scrub different blocks of memory simultaneous or in parallel… may perform memory scrubbing operations independent of each other)
As per claim 13:
Rodeheffer-Luck further discloses:
wherein the receiving of the error-related transaction values includes receiving a first set of values controlling the performing of the first error-related transaction, and receiving a second set of values controlling the performing of the second error-related transaction.
(Rodeheffer [0039] access controller 212 also initiates a remedial action when a normal memory access operation (as opposed to a scrubbing scan operation) results in detection of an error by the error detection logic 214… send a request to another device, such as the main memory controller 40 or the CPU 20 to generate a corrected memory line using the ECC code for the memory line (or for the portion of the memory line determined to have been corrupted) and to write the corrected memory line back to memory 18)
As per claim 14:
Rodeheffer-Luck further discloses:
wherein the first set of error-related transaction values specify, as the first error-related transaction, a first sequence of error correcting code (ECC) actions to be performed on select locations in the first memory block, and the second set of error-related transaction values specify, as the second error-related transaction, a second sequence of ECC actions to be performed on select locations in the second memory block.
(Rodeheffer [0039] access controller 212 also initiates a remedial action when a normal memory access operation (as opposed to a scrubbing scan operation) results in detection of an error by the error detection logic 214… send a request to another device, such as the main memory controller 40 or the CPU 20 to generate a corrected memory line using the ECC code for the memory line (or for the portion of the memory line determined to have been corrupted) and to write the corrected memory line back to memory 18)
As per claim 15:
Rodeheffer-Luck further discloses:
wherein the performing of the first error-related transaction includes:
retrieving, from the first memory block, a first set of data and a first error correcting code (ECC) syndrome; determining a second ECC syndrome for the first set of data; based on the first ECC syndrome and second ECC syndrome, correcting an error present in the first set of data to produce a second set of data; and storing the second set of data in the first memory block.
(Rodeheffer [0039] access controller 212 also initiates a remedial action when a normal memory access operation (as opposed to a scrubbing scan operation) results in detection of an error by the error detection logic 214… send a request to another device, such as the main memory controller 40 or the CPU 20 to generate a corrected memory line using the ECC code for the memory line (or for the portion of the memory line determined to have been corrupted) and to write the corrected memory line back to memory 18)
As per claim 16:
Rodeheffer-Luck further discloses:
wherein the performing of the first error-related transaction includes:
retrieving, from the first memory block, a first set of data and a first error correcting code (ECC) syndrome associated with the first error-related transaction; determining a second ECC syndrome for the first set of data; based on the first ECC syndrome and second ECC syndrome, determining whether an uncorrectable error is present in the first set of data; and generating an interrupt based on the uncorrectable error in the first set of data.
(Rodeheffer [0039] access controller 212 also initiates a remedial action when a normal memory access operation (as opposed to a scrubbing scan operation) results in detection of an error by the error detection logic 214… send a request to another device, such as the main memory controller 40 or the CPU 20 to generate a corrected memory line using the ECC code for the memory line (or for the portion of the memory line determined to have been corrupted) and to write the corrected memory line back to memory 18)
As per claim 18:
Rodeheffer-Luck further discloses:
wherein the performing of the first error-related transaction further includes: based on the first set of values: sequentially accessing select addresses in the first memory block to detect and correct one-bit errors at the select addresses.
(Rodeheffer, [0035] when a subcontroller 16 detects corrupt bits in corresponding RAM 18, the subcontroller remembers the address of the memory line containing the corrupt bits and informs CPU 20)
As per claim 19:
Rodeheffe-Luck further discloses:
wherein the performing of the first error-related transaction further includes: based on the first set of values: sequentially accessing select addresses in the first memory block until a non-correctable error is encountered; and
(Rodeheffer, [0035] when a subcontroller 16 detects corrupt bits in corresponding RAM 18, the subcontroller remembers the address of the memory line containing the corrupt bits and informs CPU 20)
terminate the first error-related transaction in response to encountering a non-correctable error.
(Rodeheffer, [0052] Error logic 614, which is coupled to the memory array (202-N-M) and code array (206-N-M), determines whether any of the portions 202-N-M of a specified memory line in the memory array is inconsistent with the corresponding error code 206-N-M. When an inconsistency is encountered, error logic 614 generates a corresponding error detection signal…)
As per claim 20:
Rodeheffer-Luck further discloses:
wherein the performing of the first error-related transaction based on the first set of values further includes
(Rodeheffer, [0052] Error logic 614, which is coupled to the memory array (202-N-M) and code array (206-N-M), determines whether any of the portions 202-N-M of a specified memory line in the memory array is inconsistent with the corresponding error code 206-N-M. When an inconsistency is encountered, error logic 614 generates a corresponding error detection signal…)
further includes providing an early termination signal.
(Rodeheffer, [0052] Error logic 614, which is coupled to the memory array (202-N-M) and code array (206-N-M), determines whether any of the portions 202-N-M of a specified memory line in the memory array is inconsistent with the corresponding error code 206-N-M. When an inconsistency is encountered, error logic 614 generates a corresponding error detection signal…)
Claims 7-8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodeheffer et al (US 2003/0,097,608), in view of Luck (US 2018/0,190,365), in view of Pierson et al (US 2016/0,162,407)
As per claim 7:
Rodeheffer-Luck further discloses:
wherein
at least one of the instances of control logic includes
a
(Rodeheffer [0039] access controller 212 also initiates a remedial action when a normal memory access operation (as opposed to a scrubbing scan operation) results in detection of an error by the error detection logic 214… send a request to another device, such as the main memory controller 40 or the CPU 20 to generate a corrected memory line using the ECC code for the memory line (or for the portion of the memory line determined to have been corrupted) and to write the corrected memory line back to memory 18)
Rodeheffe-Luck does not disclose:
a register.
Pierson discloses:
a register.
(Pierson [0090] frequency between scrubbing cycles set by the delay between each burst by Error detection and correction scrubber 659. … programmed using a configuration register. A bit field REFDEL is programmed to control the number of clock cycles between each scrub burst. This value is preferably scaled to prevent specification of too frequent scrubbing bursts reducing memory performance. Error detection and correction scrubber 659 is enabled by default at reset but may be disabled by resetting a bit in a configuration register)
(Pierson [0091] Error detection and correction scrubber 659 preferably can log errors and locally collect statistics about scrubbing errors… it preferably corrects the error to restore the data and logs the address of the error and the syndrome value identifying the erroneous bit and increments a SCEC… it logs the address and increments the SNCEC (Scrub Non-Correctable Error Counter). The SCEC and SNCED fields can be read to provide statistics on error generation. …permits adjustment of the number of clock cycles between each scrub burst based upon error rate. If the error rate is high, scrub cycles may be initiated more frequently. If the error rate is low, less frequent scrubbing may be implemented to reduce power consumption and interference with functional memory access traffic)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Pierson’s register into the system in order to log errors and locally collect statistics about scrubbing errors. As such, it would allow the system to adjust the frequency of scrubbing.
(Pierson [0090] frequency between scrubbing cycles set by the delay between each burst by Error detection and correction scrubber 659. … programmed using a configuration register. A bit field REFDEL is programmed to control the number of clock cycles between each scrub burst. This value is preferably scaled to prevent specification of too frequent scrubbing bursts reducing memory performance. Error detection and correction scrubber 659 is enabled by default at reset but may be disabled by resetting a bit in a configuration register)
(Pierson [0091] Error detection and correction scrubber 659 preferably can log errors and locally collect statistics about scrubbing errors… it preferably corrects the error to restore the data and logs the address of the error and the syndrome value identifying the erroneous bit and increments a SCEC… it logs the address and increments the SNCEC (Scrub Non-Correctable Error Counter). The SCEC and SNCED fields can be read to provide statistics on error generation. …permits adjustment of the number of clock cycles between each scrub burst based upon error rate. If the error rate is high, scrub cycles may be initiated more frequently. If the error rate is low, less frequent scrubbing may be implemented to reduce power consumption and interference with functional memory access traffic)
As per claim 8:
Rodeheffe-Luck does not disclose:
wherein each of the instances of control logic includes a
Pierson discloses:
wherein each of the instances of control logic includes a
(Pierson [0090] frequency between scrubbing cycles set by the delay between each burst by Error detection and correction scrubber 659. … programmed using a configuration register. A bit field REFDEL is programmed to control the number of clock cycles between each scrub burst. This value is preferably scaled to prevent specification of too frequent scrubbing bursts reducing memory performance. Error detection and correction scrubber 659 is enabled by default at reset but may be disabled by resetting a bit in a configuration register)
(Pierson [0091] Error detection and correction scrubber 659 preferably can log errors and locally collect statistics about scrubbing errors… it preferably corrects the error to restore the data and logs the address of the error and the syndrome value identifying the erroneous bit and increments a SCEC… it logs the address and increments the SNCEC (Scrub Non-Correctable Error Counter). The SCEC and SNCED fields can be read to provide statistics on error generation. …permits adjustment of the number of clock cycles between each scrub burst based upon error rate. If the error rate is high, scrub cycles may be initiated more frequently. If the error rate is low, less frequent scrubbing may be implemented to reduce power consumption and interference with functional memory access traffic)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Pierson’s register into the system in order to log errors and locally collect statistics about scrubbing errors. As such, it would allow the system to adjust the frequency of scrubbing.
(Pierson [0090] frequency between scrubbing cycles set by the delay between each burst by Error detection and correction scrubber 659. … programmed using a configuration register. A bit field REFDEL is programmed to control the number of clock cycles between each scrub burst. This value is preferably scaled to prevent specification of too frequent scrubbing bursts reducing memory performance. Error detection and correction scrubber 659 is enabled by default at reset but may be disabled by resetting a bit in a configuration register)
(Pierson [0091] Error detection and correction scrubber 659 preferably can log errors and locally collect statistics about scrubbing errors… it preferably corrects the error to restore the data and logs the address of the error and the syndrome value identifying the erroneous bit and increments a SCEC… it logs the address and increments the SNCEC (Scrub Non-Correctable Error Counter). The SCEC and SNCED fields can be read to provide statistics on error generation. …permits adjustment of the number of clock cycles between each scrub burst based upon error rate. If the error rate is high, scrub cycles may be initiated more frequently. If the error rate is low, less frequent scrubbing may be implemented to reduce power consumption and interference with functional memory access traffic)
As per claim 17:
Rodeheffe-Luck does not disclose:
wherein the performing of the first error-related transaction includes: based on the first set of values: providing a stall request signal upon elapse of a countdown time period; preventing execution of a non-error-related transaction on the first memory block based on the stall request signal; providing an acknowledge signal; and beginning to perform the first error-related transaction based on the acknowledge signal.
Pierson discloses:
wherein the performing of the first error-related transaction includes: based on the first set of values: providing a stall request signal upon elapse of a countdown time period; preventing execution of a non-error-related transaction on the first memory block based on the stall request signal; providing an acknowledge signal; and beginning to perform the first error-related transaction based on the acknowledge signal.
(Pierson [0090] frequency between scrubbing cycles set by the delay between each burst by Error detection and correction scrubber 659. … programmed using a configuration register. A bit field REFDEL is programmed to control the number of clock cycles between each scrub burst. This value is preferably scaled to prevent specification of too frequent scrubbing bursts reducing memory performance. Error detection and correction scrubber 659 is enabled by default at reset but may be disabled by resetting a bit in a configuration register)
(Pierson [0091] Error detection and correction scrubber 659 preferably can log errors and locally collect statistics about scrubbing errors… it preferably corrects the error to restore the data and logs the address of the error and the syndrome value identifying the erroneous bit and increments a SCEC… it logs the address and increments the SNCEC (Scrub Non-Correctable Error Counter). The SCEC and SNCED fields can be read to provide statistics on error generation. …permits adjustment of the number of clock cycles between each scrub burst based upon error rate. If the error rate is high, scrub cycles may be initiated more frequently. If the error rate is low, less frequent scrubbing may be implemented to reduce power consumption and interference with functional memory access traffic)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate Pierson’s register into the system in order to log errors and locally collect statistics about scrubbing errors. As such, it would allow the system to adjust the frequency of scrubbing.
(Pierson [0090] frequency between scrubbing cycles set by the delay between each burst by Error detection and correction scrubber 659. … programmed using a configuration register. A bit field REFDEL is programmed to control the number of clock cycles between each scrub burst. This value is preferably scaled to prevent specification of too frequent scrubbing bursts reducing memory performance. Error detection and correction scrubber 659 is enabled by default at reset but may be disabled by resetting a bit in a configuration register)
(Pierson [0091] Error detection and correction scrubber 659 preferably can log errors and locally collect statistics about scrubbing errors… it preferably corrects the error to restore the data and logs the address of the error and the syndrome value identifying the erroneous bit and increments a SCEC… it logs the address and increments the SNCEC (Scrub Non-Correctable Error Counter). The SCEC and SNCED fields can be read to provide statistics on error generation. …permits adjustment of the number of clock cycles between each scrub burst based upon error rate. If the error rate is high, scrub cycles may be initiated more frequently. If the error rate is low, less frequent scrubbing may be implemented to reduce power consumption and interference with functional memory access traffic)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIEN DANG NGUYEN whose telephone number is (571)272-9189. The examiner can normally be reached Monday-Friday 7 AM - 3:30 PM.
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/Thien Nguyen/ Primary Examiner, Art Unit 2111