Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the application filed on 01/23/2025. Currently, claims 1-25 are pending.
The current application is a continuation of application 17/665,398 (U.S. Patent No. 12,148,824), which itself is a division of application 16/528,41 (U.S. Patent No. 11,251,296).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 7, 21 and 24 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 6, 15-17, 20-23 of U.S. Patent No. 11,251,296 in view of Yilmaz (Pub. No. US 2019/0348510 A1).
Regarding claim 1, claims 1-2, 6, 15-17, 20-23 of U.S. Patent No. 11,251,296 disclose the limitations of claims 1, 7, 21 and 24 except for the positions of the first and second shielding regions being spaced from the first and second gate electrodes by the gate dielectric layers; and the first surfaces of the substrate, the body region and the source region being coplanar with each other.
However, in the same field of endeavor, Yilmaz discloses a device, comprising: a substrate 10/12 ([0020]) having a first surface (See Figs. 1A-2B, the top surface of the substrate 10/12); a body region 14 ([0020]) in the substrate; a source region 17 ([0020]) in the body region; a first trench “T1” and a second trench “T2” in the substrate (See Figs. 1A-2B and [0020]-[0021]), the first trench and the second trench extending through the body region and the source region (See Figs. 1A-2B), the first trench having a first end (the bottom end) in the substrate, the second trench having a second end (the bottom end) in the substrate; a first gate dielectric 20-24 on sidewalls and a bottom of the first trench “T1” (See Figs. 1A-2B and [0021]); a second gate dielectric 20-24 on sidewalls and a bottom of the second trench “T2” (See Figs. 1A-2B and [0021]); a first gate electrode 26 on the first gate dielectric in the first trench (See Figs. 1A-2B and [0021]), a first surface of the first gate electrode being coplanar with the first surface of the substrate (See Figs. 1A-2B, 5H and [0040]); a second gate electrode 26 on the second gate dielectric in second trench (See Figs. 1A-2B and [0021]), a first surface of the second gate electrode being coplanar with the first surface of the substrate (See Figs. 1A-2B, 5H and [0040]); a first shielding region 18-16 ([0020]-[0021]) at the first end of the first trench “T1”, in the substrate, the first shielding region being spaced from the first gate electrode 26 by only the first gate dielectric 20-24 (See Figs. 1A-2B); and a second shielding region 18-16 ([0020]-[0021]) at the second end of the second trench “T2”, in the substrate, the first shielding region being spaced from the second gate electrode 26 by only the second gate dielectric (See Figs. 1A-2B), wherein the first surface of the substrate is coplanar with a first surface of the body region and a first surface of the source region (See the below illustration and [0020]-[0021]) to resolve reliability and fabrication challenges of the thick shielded gate structures ([0019]).
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Therefore, given the teachings of Yilmaz, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the claims of U.S. Patent No. 11,251,296 in view of Yilmaz by employing the above explained configuration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yilmaz (Pub. No. US 2019/0348510 A1).
Regarding claim 1, Yilmaz discloses a device, comprising: a substrate 10/12 ([0020]) having a first surface (See Figs. 1A-2B, the top surface of the substrate 10/12); a body region 14 ([0020]) in the substrate; a source region 17 ([0020]) in the body region; a first trench “T1” and a second trench “T2” in the substrate (See Figs. 1A-2B and [0020]-[0021]), the first trench and the second trench extending through the body region and the source region (See Figs. 1A-2B), the first trench having a first end (the bottom end) in the substrate, the second trench having a second end (the bottom end) in the substrate; a first gate dielectric 20-24 on sidewalls and a bottom of the first trench “T1” (See Figs. 1A-2B and [0021]); a second gate dielectric 20-24 on sidewalls and a bottom of the second trench “T2” (See Figs. 1A-2B and [0021]); a first gate electrode 26 on the first gate dielectric in the first trench (See Figs. 1A-2B and [0021]), a first surface of the first gate electrode being coplanar with the first surface of the substrate (See Figs. 1A-2B, 5H and [0040]); a second gate electrode 26 on the second gate dielectric in second trench (See Figs. 1A-2B and [0021]), a first surface of the second gate electrode being coplanar with the first surface of the substrate (See Figs. 1A-2B, 5H and [0040]); a first shielding region 18-16 ([0020]-[0021]) at the first end of the first trench “T1”, in the substrate, the first shielding region being spaced from the first gate electrode 26 by only the first gate dielectric 20-24 (See Figs. 1A-2B); and a second shielding region 18-16 ([0020]-[0021]) at the second end of the second trench “T2”, in the substrate, the first shielding region being spaced from the second gate electrode 26 by only the second gate dielectric (See Figs. 1A-2B).
Regarding claim 2, Yilmaz discloses the device of claim 1, wherein the substrate 10-12 has a first conductivity type ([0020]; n-type), the body region 14 has a second conductivity type ([0020]; p-type) different from the first conductivity type, and the first and second shielding regions 18-16 have the second conductivity type (See Figs. 1A-2B and [0020]-[0021]; p-type).
Regarding claim 3, Yilmaz discloses the device of claim 1, wherein the first surface of the substrate is coplanar with a first surface of the body region and a first surface of the source region (See the above illustration and [0020]-[0021]).
Regarding claim 4, Yilmaz discloses the device of claim 1, wherein the first gate region is a single, continuous region of a conductive material (See the above illustration and [0020]-[0021]).
Regarding claim 5, Yilmaz discloses the device of claim 1, comprising a first dielectric layer 28 on the first surface of the substrate, the first dielectric layer being directly coupled to the first gate dielectric and the first gate electrode (See Figs. 1A-2B and [0022]).
Regarding claim 6, Yilmaz discloses the device of claim 5, wherein the first dielectric layer has a first dimension along a first direction greater than a second dimension of the first trench along the first direction (See Figs. 1A-2B and [0022]).
Regarding claim 7, Yilmaz discloses a device, comprising: a substrate 10-12 having a first surface (See Figs. 1A-2B and [0020]; top surface) opposite a second surface along a first direction (vertical direction); a body region 14 (See Figs. 1A-2B and [0020]) in the substrate extending from the first surface of the substrate into the substrate along the first direction, the body region having a first surface coplanar with the first surface of the substrate (See the above illustration); a source region 17 (See Figs. 1A-2B and [0020]) in the substrate extending from the first surface of the substrate into the body region along the first direction, the source region having a first surface coplanar with the first surface of the substrate (See the above illustration); a first trench “T1” in the substrate, the first trench extending along the first direction through the body region and the source region (See Figs. 1A-2B and [0020]), the first trench having a first end (bottom end) in the substrate and a first dimension along a second direction (horizontal direction) transverse to the first direction; a first gate dielectric 20-24 in the first trench “T1” (See Figs. 1A-2B and [0021]), the first gate dielectric covering the first end and a first plurality of sidewalls of the first trench; a first gate electrode 26 (See Figs. 1A-2B and [0021]) on the first gate dielectric in the first trench, a first surface of the first gate electrode being coplanar with the first surface of the substrate and the first surface of the source region (See the the above illustration); a first dielectric layer 28 (See Figs. 1A-2B and [0022]) on the first surface of the substrate, the first dielectric layer having a second dimension along the second direction (horizontal direction) greater than the first dimension; and a first shielding region 18-16 (See Figs. 1A-2B and [0021]) at the first end of the first trench, in the substrate, the first shielding region being spaced from the first gate electrode along the first direction by the first gate dielectric, a central axis of the first shielding region being aligned with a central axis of the first gate electrode and a central axis of the first trench along the first direction (See the above illustration).
Regarding claim 8, Yilmaz discloses the device of claim 7, further comprising: a second trench “T2” (See Figs. 1A-2B and [0021]) in the substrate, the second trench extending along the first direction (vertical direction) through the body region 14 and the source region 17 (See Figs. 1A-2B and [0020]), the second trench having a second end (bottom end) in the substrate, the second trench having a third dimension along the second direction (horizontal direction); a second gate dielectric 20-24 (See Figs. 1A-2B and [0021]) in the second trench, the second gate dielectric covering the second end and a second plurality of sidewalls of the second trench (See Figs. 1A-2B); a second gate electrode 26 on the second gate dielectric in the second trench (See Figs. 1A-2B and [0021]), a first surface of the second gate electrode being coplanar with the first surface of the substrate (See the above illustration); a second dielectric layer 28 on the first surface of the substrate, the second dielectric layer having a fourth dimension along the second direction greater than the first and third dimensions; and a second shielding region at the second end of the second trench, in the substrate (See the above illustration), the first shielding region 18-16 being spaced from the second gate electrode along the first direction by the second gate dielectric (See Figs. 1A-2B and [0021]).
Regarding claim 9, Yilmaz discloses the device of claim 8, wherein the source region 17 includes a first portion with a first surface extending along the first direction (vertical direction) and a second surface extending along the second direction (horizontal direction), the first surface of the first portion being directly coupled to the first gate dielectric and the second surface of the first portion being directly coupled to the first dielectric layer (See Figs. 1A-2B and [0021]).
Regarding claim 10, Yilmaz discloses the device of claim 9, wherein the source region 17 includes a second portion with a first surface extending along the first direction and a second surface extending along the second direction, the first surface of the second portion being directly coupled to the second gate dielectric 20-24 and the second surface of the second portion being directly coupled to the second dielectric layer 28 (See Figs. 1A-2B and [0021]).
Regarding claim 11, Yilmaz discloses the device of claim 10, wherein the second surface of the first portion and the second surface of the second portion are coplanar with the first surface of the substrate (See the above illustration).
Regarding claim 12, Yilmaz discloses the device of claim 7, further comprising a source electrode 30-32 on the first surface of the substrate, the source electrode being directly coupled to the body region, the source region, and the first dielectric layer (See Figs. 1A-2B and [0022]).
Regarding claim 13, Yilmaz discloses the device of claim 12, further comprising a drain electrode on the second surface of the substrate ([0020]; “A drain contact may be on the bottom of MOSFET 100, particularly on a bottom surface of N+ substrate 10, and an electrical contact between N+ substrate 10 and a metal contact pad/layer (not shown) could be ohmic.”).
Regarding claim 14, Yilmaz discloses the device of claim 8, wherein the first and third dimensions are substantially equal (See Figs. 1A-2B).
Regarding claim 15, Yilmaz discloses the device of claim 7, wherein the first shielding region has a third dimension along the second direction smaller than the first dimension (See Figs. 1A-2B).
Regarding claim 16, Yilmaz discloses the device of claim 15, wherein the third dimension of the first shielding region is greater than a fourth dimension along the second direction of the first gate electrode (See Figs. 1A-2B).
Regarding claim 17, Yilmaz discloses the device of claim 7, wherein the first plurality of sidewalls of the first trench extend along the first direction substantially perpendicular to the first surface of the substrate (See Figs. 1A-2B).
Regarding claim 18, Yilmaz discloses the device of claim 7, wherein the first gate dielectric has a first portion covering the first end with a first thickness along the first direction and a second portion covering a first sidewall of the first plurality of sidewalls with a second thickness along the second direction, the first thickness being substantially equal to the second thickness (See Figs. 1A-2B).
Regarding claim 19, Yilmaz discloses the device of claim 7, wherein the first gate dielectric layer has a first surface coplanar with the first surface of the substrate (See the above illustration).
Regarding claim 20, Yilmaz discloses the device of claim 8, wherein the first gate electrode 26 is separated from the first shielding region 18-16 by only the first gate dielectric layer and the second gate electrode 26 is separated from the second shielding region 18-16 by only the second gate dielectric layer (See Figs. 1A-2B).
Regarding claim 21, Yilmaz discloses a device, comprising: a substrate 10-12 having a first surface (top surface) opposite to a second surface; a body region 14 in the substrate (See Figs. 1A-2B and [0020]); a source region 17 in the body region (See Figs. 1A-2B and [0020]); a first trench “T1” with substantially parallel sidewalls (See Figs. 1A-2B and [0020]), the first trench being in the substrate and extending through the body region and through the source region (See Figs. 1A-2B and [0020]); a first shielding region 18-16 in the substrate at an end of the first trench (See Figs. 1A-2B and [0021]); a first gate dielectric layer 20-24 on the sidewalls and a bottom of the first trench (See Figs. 1A-2B and [0020]), the first gate dielectric layer having a first surface coplanar with the first surface of the substrate (See the above illustration); a first gate electrode 26 in the first trench, the first gate electrode extending from the end of the first trench to the first surface of the substrate (See Figs. 1A-2B and [0021]).
Regarding claim 22, Yilmaz discloses the device of claim 21, wherein the source region 17 includes a first surface coplanar with the first surface of the substrate and a second surface transverse to the first surface of the source region, the second surface being on the first gate dielectric (See the above illustration).
Regarding claim 23, Yilmaz discloses the device of claim 21, further comprising a drain electrode on the second surface of the substrate and a source electrode on the first surface of the substrate, the source electrode being directly coupled to the source region and the body region ([0020]; “A drain contact may be on the bottom of MOSFET 100, particularly on a bottom surface of N+ substrate 10, and an electrical contact between N+ substrate 10 and a metal contact pad/layer (not shown) could be ohmic.”).
Regarding claim 24, Yilmaz discloses a device, comprising: a substrate 10-12 having a first surface (top surface) opposite a second surface along a first direction (vertical direction); a body region 14 (See Figs. 1A-2B and [0020]) in the substrate extending from the first surface of the substrate into the substrate along the first direction, the body region having a first surface coplanar with the first surface of the substrate (See the above illustration); a source region 17 (See Figs. 1A-2B and [0020]) in the substrate extending from the first surface of the substrate into the body region along the first direction, the source region having a first surface coplanar with the first surface of the substrate (See the the above illustration); a first trench “T1” and a second trench “T2” (See Figs. 1A-2B and [0020]) in the substrate, the first trench and the second trench extending along the first direction through the body region and the source region, the first trench having a first end in the substrate, the second trench having a second end in the substrate, the first trench having a first dimension along a second direction transverse to the first direction, the second trench having a second dimension along the second direction (See Figs. 1A-2B and [0020]); a first gate dielectric 20-24 in the first trench, the first gate dielectric covering the first end and a first plurality of sidewalls of the first trench (See Figs. 1A-2B and [0021]); a second gate dielectric 20-24 in the second trench, the second gate dielectric covering the second end and a second plurality of sidewalls of the second trench (See Figs. 1A-2B and [0021]); a first gate electrode 26 on the first gate dielectric in the first trench, a first surface of the first gate electrode being coplanar with the first surface of the substrate (See Figs. 1A-2B and [0021]); a second gate electrode 26 on the second gate dielectric in the second trench, a first surface of the second gate electrode being coplanar with the first surface of the substrate (See Figs. 1A-2B and [002]); a first dielectric layer 28 on the first surface of the substrate, the first dielectric layer having a third dimension along the second direction greater than the first dimension (See Figs. 1A-2B and [0022]); a second dielectric layer 28 on the first surface of the substrate, the second dielectric layer having a fourth dimension along the second direction greater than the second dimension (See Figs. 1A-2B and [0022]); a first shielding region 18-16 at the first end of the first trench, in the substrate, the first shielding region being spaced from the first gate electrode along the first direction by the first gate dielectric (See Figs. 1A-2B and [0021]); and a second shielding region 18-16 at the second end of the second trench, in the substrate, the first shielding region being spaced from the second gate electrode along the first direction by the second gate dielectric (See Figs. 1A-2B and [0021]).
Regarding claim 25, Yilmaz discloses the device of claim 24, wherein the substrate 10-12 has a first conductivity type ([0020]; n-type), the body region 14 has a second conductivity type ([0020]; p-type) different from the first conductivity type, and the first and second shielding regions 18-16 have the second conductivity type (See Figs. 1A-2B and [0020]-[0021]; p-type).
Prior Art
The prior arts made of record and not relied upon are considered pertinent to applicant’s disclosure. For example:
Zeng et al. (Pub. No. US 2016/0359029 A1) discloses a power MOSFET cell includes an N+ silicon substrate having a drain electrode; an N-type drift layer grown over the substrate; an N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls; a P-well is formed in the N-type layer, and an N+ source region is formed in the P-well; a gate is formed over the P-well's lateral channel and has a vertical extension into the trench; a vertical shield field plate is also located next to the sidewalls and may be connected to the gate; the field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage; and a buried layer and sinker enable the use of a topside drain electrode.
Conclusion
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September 30, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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