Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 21-40 are presented for examination.
Claims 1-20 are cancelled.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-23 of U.S. Patent No. 12,141,268. Although the claims at issue are not identical, they are not patentably distinct from each other.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-22, 25-27, 29-37, and 39-40 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by LIU et al hereafter LIU (US pat. App. Pub. 20210173934).
5. As per claims 21, and 27, LIU teaches a computer-implemented method, a system comprising: causing a processor associated with a parallel processing unit (PPU) to allocate a protected memory region within the PPU (Fig. 6, and Fig. 17, paragraphs: 2, and 46, wherein it emphasizes that establishes connection through a trusted execution environment (TEE) to the data processing (DP) accelerator which act as parallel processing unit (PPU). This DP accelerator has the processing unit and creates protected memory); and preventing software executed by a central processing unit (CPU) from accessing data transmitted from the CPU to the protected memory region by at least causing the data to be encrypted based, at least in part, on a cryptographic key associated with the PPU (Fig. 10, paragraphs: 52, 64, 97-98, and 103, wherein it elaborates that the software running in the main processor is restricted to access data from the protected memory region of the DP accelerator as the data inside the protected memory region is encrypted by using the encryption key associated with the DP accelerator).
6. As per claim 22, LIU teaches the computer-implemented method, further comprising: causing the processor to negotiate the cryptographic key with the CPU based, at least in part, on a private key specific to the PPU (paragraphs: 42-44, 51-54, wherein it deliberates that the processing unit of the DP accelerator (PPU) establishes a session key with main processor based on the private key that is associated with the DP accelerator (PPU)).
7. As per claim 25, LIU teaches the computer-implemented method, further comprising: in response to a request to disable a secure execution mode of the PPU, causing the processor to delete the cryptographic key and information stored in the protected memory region (paragraphs 97-98, 104, and 107, wherein it describes when the DP accelerator (PPU) is disabled then the session key will be destroyed upon the request from processor).
8. As per claim 26, LIU teaches the computer-implemented method, wherein the software comprises a hypervisor that provides a trusted execution environment (TEE) (paragraphs: 46, 64, and 72).
9. As per claim 29, LIU teaches the system, wherein the instructions further comprise instructions that, in response to execution by the one or more first processors, cause the system to at least: store the data that is encrypted in a memory region of the PPU that is separate from the protected memory region; cause the second processor associated with the PPU to decrypt the data that is encrypted based, at least in part, on the cryptographic key; and store the decrypted data in the protected memory region (paragraphs: 73-74, 130, and 140).
10. As per claim 30, LIU teaches the system, wherein the instructions further comprise instructions that, in response to execution by the one or more first processors, cause the system to at least: cause the second processor associated with the PPU to negotiate the cryptographic key with the CPU based, at least in part, on a security protocol executed by the CPU (paragraphs: 42-44, 51-54).
11. As per claim 31, LIU teaches the system, wherein the instructions further comprise instructions that, in response to execution by the one or more first processors, cause the system to at least: generate an attestation of a state of the PPU based, at least in part, on the cryptographic key (paragraphs: 58-59, and 153-154).
12. As per claim 32, LIU teaches the system, wherein the cryptographic key is stored in a write-once memory (paragraphs: 120-123).
13. As per claim 33, LIU teaches the system, wherein the second processor associated with the PPU comprises a secure processor that prevents the CPU from accessing the protected memory region (paragraphs: 126-127).
14. As per claim 34, LIU teaches the system, wherein the data comprises one or more weights of a machine learning model (paragraphs: 63-64, and 75).
15. As per claim 35, LIU teaches the system, wherein the cryptographic key is usable to isolate the software from an operating system that is part of a trusted execution environment (TEE) (paragraphs: 46, and 69).
16. As per claim 36, LIU teaches the system, wherein the PPU comprises a graphics processing unit (GPU) (paragraphs: 46, and 82).
17. As per claim 37, LIU teaches a parallel processing unit (PPU) comprising: a secure processor; a protected memory region that is allocated by the secure processor (Fig. 6, and Fig. 17, paragraphs: 2, and 46, wherein it emphasizes that establishes connection through a trusted execution environment (TEE) to the data processing (DP) accelerator which act as parallel processing unit (PPU). This DP accelerator has the processing unit and creates protected memory); and a cryptographic key usable to prevent software executed by a central processing unit (CPU) from accessing data transmitted from the CPU to the protected memory region by at least encrypting the data (Fig. 10, paragraphs: 52, 64, 97-98, and 103, wherein it elaborates that the software running in the main processor is restricted to access data from the protected memory region of the DP accelerator as the data inside the protected memory region is encrypted by using the encryption key associated with the DP accelerator).
18. As per claim 39, LIU teaches the PPU, further comprising: a memory management unit (MMU) that prevents the CPU from accessing the protected memory region (paragraphs: 83-83).
19. As per claim 40, LIU teaches the PPU, wherein the PPU is to: store, in a memory region of the PPU that is separate from the protected memory region, encrypted data transmitted from the CPU; decrypt the encrypted data based, at least in part, on the cryptographic key; and store the decrypted data in the protected memory region (paragraphs: 86-88, 100-102).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
20. Claims 23-24, 28, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over LIU et al hereafter LIU (US pat. App. Pub. 20210173934) and in view of Hoogerbrugge et al hereafter Hoogerbrugge (US pat. App. Pub. 20220129566).
21. As per claim 23, LIU discloses the computer-implemented method, further comprising: storing the data that is encrypted in a memory region of the PPU that is separate from the protected memory region (paragraphs:82-83, and 88). He does not expressly disclose causing the processor to decrypt the data that is encrypted based, at least in part, on the cryptographic key; and storing the decrypted data in the protected memory region. However, in the same field of endeavor, Hoogerbrugge discloses causing the processor to decrypt the data that is encrypted based, at least in part, on the cryptographic key; and storing the decrypted data in the protected memory region (paragraphs: 10-11, and 15-16).
Accordingly, it would been obvious to one of ordinary skill in the network security art before the effective filing date of the claimed invention to have incorporated Hoogerbrugge’s teachings of causing the processor to decrypt the data that is encrypted based, at least in part, on the cryptographic key; and storing the decrypted data in the protected memory region with the teachings of LIU, for the purpose of effectively protecting the sensitive information from any unauthorized intruders.
22. As per claim 24, LIU discloses the computer-implemented method, further comprising: as a result of one or more engines of the PPU performing a read operation on a set of data stored in the protected memory region (129-132). He does not expressly discloses preventing the one or more engines from executing a write operation outside of the protected memory region. However, in the same field of endeavor, Hoogerbrugge discloses preventing the one or more engines from executing a write operation outside of the protected memory region (paragraphs: 15-16).
Accordingly, it would been obvious to one of ordinary skill in the network security art before the effective filing date of the claimed invention to have incorporated Hoogerbrugge’s teachings of preventing the one or more engines from executing a write operation outside of the protected memory region with the teachings of LIU, for the purpose of effectively securing the protected memory region from any unauthorized writing or storing information inside the protected memory region.
23. As per claim 28, LIU discloses the system, wherein the instructions further comprise instructions that, in response to execution by the one or more first processors, cause the system to at least: in response to one or more engines of the PPU executing one or more read operations on a set of data stored in the protected memory region (129-132). He does not expressly discloses cause the one or more engines to be prevented from executing one or more operations outside of the protected memory region. However, in the same field of endeavor, Hoogerbrugge discloses cause the one or more engines to be prevented from executing one or more operations outside of the protected memory region (paragraphs: 15-16).
Accordingly, it would been obvious to one of ordinary skill in the network security art before the effective filing date of the claimed invention to have incorporated Hoogerbrugge’s teachings of cause the one or more engines to be prevented from executing one or more operations outside of the protected memory region with the teachings of LIU, for the purpose of effectively securing the protected memory region from any unauthorized writing or storing information inside the protected memory region.
24. As per claim 38, LIU discloses the PPU, further comprising: one or more compute units that are prevented as a result of executing a read operation on data stored in the protected memory region. (129-132). He does not expressly discloses compute units that are prevented from executing write operations outside of the protected memory region. However, in the same field of endeavor, Hoogerbrugge discloses compute units that are prevented from executing write operations outside of the protected memory region (paragraphs: 15-16).
Accordingly, it would been obvious to one of ordinary skill in the network security art before the effective filing date of the claimed invention to have incorporated Hoogerbrugge’s teachings of compute units that are prevented from executing write operations outside of the protected memory region with the teachings of LIU, for the purpose of effectively securing the protected memory region from any unauthorized writing or storing information inside the protected memory region.
Conclusion
25. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD W REZA whose telephone number is (571)272-6590. The examiner can normally be reached on Monday-Friday 8:30-5:30 ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Cathy Thiaw can be reached on 571-270-1138. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/MOHAMMAD W REZA/Primary Examiner, Art Unit 2407