Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In reply to the Non-Final office action mailed on 12/4/2025, the applicant has filed a response on 3/4/2026 amending claims 1-2 and 15-16, and Fig. 2 of the Specification. No claim has been added or cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8 and 12-19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2019/0057650), in view of Kuang et al. (US 2023/0419904), and further in view of Park et al. (US 2013/0286003).
Regarding claim 1, Choi discloses a display device (para[0012]; para[0044]; see organic light emitting display device in Fig. 1) comprising:
pixels connected to scan lines, data lines, and emission control lines (para[0012]; para[0044]; see organic light emitting display device in Fig. 1);
a start signal generator (see timing controller 140 in Fig. 1) configured to generate:
a first start signal comprising a sub-first start signal and a sub-second start
signal corresponding to a first emission control signal supplied in a first period of a frame period (para[0012]; para[0048]; para[0051]; para[0054]; para[0067]; para[0102]; para[0108]-para[0109]; para[0114]-para[0115]; “the timing controller 140 may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS”; see e.g. first period during which emission start signal ESP is provided, as shown in Fig. 2B; see emission start signals ESP provided during periods of SF1 and SF2 corresponding to periods T1 and T2 during which emission control signals E are supplied (claimed sub-first start signal and sub-second start signal), as shown in Fig. 8); and
a second start signal corresponding to a second emission control signal supplied in a second period of the frame period, and having a width that is different from a width of the first start signal (para[0012]; para[0048]; para[0051]; para[0054]; para[0067]; para[0102]; para[0117]-para[0118]; para[0120]-para[0122]; “the timing controller 140 may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS”; see e.g. second period during which emission start signal ESP is provided, as shown in Fig. 2B; see emission start signals ESP provided during periods of SF3 and SF4 corresponding to periods T3 and T4 during which emission control signals E are supplied, as shown in Fig. 8, and having width(s) different from the widths of emission start signals ESP provided during periods of SF1 and SF2);
a selector configured to supply the first start signal or the second start signal based on a control signal from a controller (para[0012]; para[0048]; para[0062]; para[0064]; regarding Fig. 1, “the timing controller 140 may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS” from controller 170, thus performing as the claimed selector); and
an emission driver configured to supply the first emission control signal or the second emission control signal to the emission control lines based on the first start
signal or the second start signal (para[0012]; para[0051]; para[0054]; para[0066]; para[0069]; see emission driver 130 in Fig. 1 “configured to supply emission control signals to the emission control lines in response to the emission start signals”).
However, Choi does not appear to expressly disclose the first emission control signal supplied in a write period of a frame period, in which a data signal is supplied; and the second emission control signal supplied in a maintenance period of the frame period, in which the data signal is maintained; the selector configured to concurrently receive the first start signal and the second start signal from the start signal generator.
Kuang discloses a first emission control signal supplied in a write period of a frame period, in which a data signal is supplied (para[0008]; para[0038]-para[0039]; para[0042]-para[0043]; para[0047]; regarding Fig. 3, see light emission control signal at terminal E supplied during light-emitting periods c1/B01 of data writing phase T1, and data signal terminal Vdata (see Fig. 2) inputs a data voltage to node N1 during data writing period b of the data writing phase T1), and a second emission control signal supplied in a maintenance period of the frame period, in which the data signal is maintained (para[0008]; para[0038]-para[0039]; para[0045]; para[0047]; regarding Fig. 3, see light emission control signal at terminal E supplied during light-emitting periods c2/Bij of data holding phases T2; “In the second light-emitting period c2, the potential of the first node N1 is maintained by the storage capacitor Cst” (see Fig. 2)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Choi’s invention, with the teachings in Kuang’s invention, to have a first start signal corresponding to a first emission control signal supplied in a write period of a frame period, in which a data signal is supplied; and a second start signal corresponding to a second emission control signal supplied in a maintenance period of the frame period, in which the data signal is maintained, and having a width that is different from a width of the first start, for the advantage of compensating for brightness reduction of the light-emitting element in the data holding/maintenance period due to leakage current, and consequently improving brightness consistency between the data write period and the data holding/maintenance period, thereby alleviating flicker problems (para[0013]).
The combination of Choi and Kuang does not appear to expressly disclose the selector configured to concurrently receive the first start signal and the second start signal from the start signal generator.
Park discloses a selector configured to concurrently receive a first start signal and a second start signal from a start signal generator (para[0051]; multiplexer 226 simultaneously receives start pulse signal SP2 and start pulse signal SP3 from logic controller 210, and provides one of the start pulse signal SP2 or the start pulse signal SP3 in response to the resolution control signal RESOL).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Choi’s and Kuang’s combination, with the teachings in Park’s invention, to have the selector configured to concurrently receive the first start signal and the second start signal from the start signal generator, for the advantage of reduced circuitry to reduce manufacturing costs (para[0003]).
Regarding claim 2, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 1). In addition, Choi discloses of the sub-second start signal is suspended after the sub-first start signal is supplied is the width of the first start signal (para[0108]-para[0109]; para[0114]-para[0115]; see e.g. in Fig. 8 the first emission start signal comprises ESP supplied with a width W1 so that pixels PXL emit light during T1 (claimed sub-first start signal) of SF1, and ESP supplied with a width W2 so that pixels PXL emit light during T2 (claimed sub-second start signal) of SF2; and wherein a time at which supply of the sub-second start signal is suspended (end of W2) after the sub-first start signal is supplied (start of W1) is the width of the claimed first emission start signal during sF1 and SF2, as shown in Fig. 8).
Regarding claim 3, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 1). In addition, the combination discloses the selector is configured to supply the first start signal to the emission driver during the write period, and to supply the second start signal to the emission driver during the maintenance period (regarding Figs. 2B and 8 of Choi, “the timing controller 140 may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS”; as already shown by the combination, this plurality of emission start signals with different widths are provided during the data writing phase T1 and the data holding phases T2 of Kuang (Figs. 3-4), correspondingly).
Regarding claim 4, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 1). In addition, in the combination, Choi discloses the widths of the first start signal and the second start signal are set such that light is generated in the pixels during the write period and the maintenance period to have a luminance difference equal to or less than a threshold value (para[0009]-para[0010]; para[0100]-para[0103]; para[0130]; “the one frame 1F period is divided into the plurality of sub-periods SF1, SF2, SF3, and SF4 and the emission time of the pixel PXL is set to vary in each sub-period” according to the widths of the emission start signals ESP, in order “to minimize the difference in brightness between the former half and the latter half of the one frame 1F period [write and maintenance periods in the combination] so that it is possible to improve display quality”, this minimum difference corresponding to a certain difference so small that e.g. prevents a flicker phenomenon (claimed threshold value), based on the broadest reasonable interpretation of the claimed limitations).
Regarding claim 5, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 4). In addition, Kuang discloses the pixels emit light for a longer time during the write period as compared with the maintenance period (e.g. as shown in Fig. 3, based on the broadest reasonable interpretation of the claimed limitations, “the duration B01 of the first-one first light-emitting period c1 in the data writing phase T1” is more than the duration Bij of any one of the at least one second light-emitting period c2 in the data holding phase T2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the widths of the first start signal and the second start signal [in the combination] are set such that the pixels emit light for a longer time during the write period as compared with the maintenance period, for the advantage of eliminating an impact of a signal input in a previous frame (that is, during a previous working cycle T), in the current working cycle T (para[0041]).
Regarding claim 6, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 4). In addition, in the combination, Choi discloses the widths of the first start signal and the second start signal are set such that the pixels emit light for a shorter time during the first period [write period in the combination] as compared with the second period [maintenance period in the combination] (see e.g. in Fig. 8, the width W1 and W2 of the first period are set such that the pixels PXL emit light during periods T1 and T2 of the first period, which are shorter than periods T3 and T4 of the second period).
Regarding claim 8, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 1). In addition, Choi discloses a timing controller configured to control the emission driver, and comprising the start signal generator, the controller, and the selector (para[0048]; para[0062]; para[0064]; see timing controller in Fig. 1, comprising the start signal generator as discussed above, controls the emission driver 130, “…may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS” from controller 170, thus performing as the claimed selector, wherein “the controller 170 may be included in the timing controller 140”).
Regarding claim 12, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 1). In addition, Choi discloses the start signal generator is configured to change the widths of the first start signal or the second start signal, corresponding to a dimming level (since the emission times of the pixel PXL during times T are controlled by the widths W, the timing controller 140 is configured to change the widths W which correspond to brightness/dimming levels, as shown in Fig. 8 such that the user may not recognize brightness differences between periods; para[0048]; para[0103]; para[0123]).
Regarding claim 13, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 1). In addition, in the combination, Choi discloses the start signal generator is configured to supply the first start signal or the second start signal to the selector during the write period or the maintenance period (para[0012]; para[0048]; regarding Fig. 1, “the timing controller 140 may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS” from controller 170 during periods with width W shown in Fig. 8, the controller 170 including the claimed selector as discussed above).
Regarding claim 14, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 1). In addition, the combination discloses the start signal generator is configured to: supply the first start signal or the second start signal to the selector [during the write period in the combination] (regarding Figs. 2B and 8 of Choi, “the timing controller 140 may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS” during W1/W2, and as already shown by the combination, first emission start signals are provided during the data writing phase T1 of Kuang), the controller 170 including the claimed selector as discussed above); and supply the second start signal to the selector during the maintenance period (regarding Figs. 2B and 8 of Choi, “the timing controller 140 may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS” during W3/W4, and as already shown by the combination, second emission start signals are provided during the data the data holding phases T2 of Kuang (Figs. 3-4), the controller 170 including the claimed selector as discussed above).
Regarding claim 15, it is analogous to claim 1, except it is a method claim (see para[0002], para[0010] and Figs. 1-4 and 8 of Choi; see para[0005], para[0009]-para[0010] and Figs. 1-4 of Kuang; see Fig. 5 of Park), and thus it is rejected for similar reasons as claim 1 above over Choi, in view of Kuang and Park.
Regarding claim 16, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 15). In addition, in the combination, Choi discloses generating the first start signal and the second start signal (see e.g. first period during which emission start signal ESP is generated, as shown in Fig. 2B, and see emission start signals ESP generated during periods of SF1 and SF2 corresponding to periods T1 and T2 during which emission control signals E are supplied, as shown in Fig. 8; see e.g. second period during which emission start signal ESP is generated, as shown in Fig. 2B, and see emission start signals ESP generated during periods of SF3 and SF4 corresponding to periods T3 and T4 during which emission control signals E are supplied, as shown in Fig. 8, and having width(s) W3/W4 different from the widths W1/W2 of emission start signals ESP provided during periods of SF1 and SF2); supplying the first start signal to the emission driver [during the write period in the combination], using [[a]] the selector (regarding Figs. 2B and 8 of Choi, “the timing controller 140 may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS”; as already shown by the combination, these emission start signals are provided during the data writing phase T1 of Kuang (Figs. 3-4)); and supplying the second start signal to the emission driver [during the maintenance period in the combination], using the selector (regarding Figs. 2B and 8 of Choi, “the timing controller 140 may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS”; as already shown by the combination, these emission start signals are provided during the data holding phases T2 of Kuang (Figs. 3-4)).
Regarding claim 17, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 15). In addition, in the combination, Choi discloses widths of the first start signal and the second start signal are set such that light is generated during the first emission period and the second emission period with a luminance difference equal to or less than a threshold value (para[0009]-para[0010]; para[0100]-para[0103]; para[0130]; “the one frame 1F period is divided into the plurality of sub-periods SF1, SF2, SF3, and SF4 and the emission time of the pixel PXL is set to vary in each sub-period” according to the widths of the emission start signals ESP, in order “to minimize the difference in brightness between the former half and the latter half of the one frame 1F period [write and maintenance periods in the combination] so that it is possible to improve display quality”, this minimum difference corresponding to a certain difference so small that e.g. prevents a flicker phenomenon (claimed threshold value), based on the broadest reasonable interpretation of the claimed limitations).
Regarding claim 18, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 17). In addition, in the combination, Choi discloses the second emission period is longer than the first emission period (see e.g. in Fig. 8, the width W1 and W2 of the first period are set such that the pixels PXL emit light during periods T1 and T2 of the first period, which are shorter than periods T3 and T4 of the second period).
Regarding claim 19, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 17). In addition, Kuang discloses the first emission period is longer than the second emission period (e.g. as shown in Fig. 3, based on the broadest reasonable interpretation of the claimed limitations, “the duration B01 of the first-one first light-emitting period c1 in the data writing phase T1” is more than the duration Bij of any one of the at least one second light-emitting period c2 in the data holding phase T2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the first emission period is longer than the second emission period, for the advantage of eliminating an impact of a signal input in a previous frame (that is, during a previous working cycle T), in the current working cycle T (para[0041]).
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2019/0057650), in view of Kuang et al. (US 2023/0419904) and Park et al. (US 2013/0286003), and further in view of Jeon et al. (US 2022/0343848).
Regarding claim 7, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 1). In addition, Choi discloses the start signal generator is configured to change a width of the first start signal or the second start signal (para[0012]; para[0048]; regarding Fig. 1, “the timing controller 140 may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS”, as shown in Fig. 8 for ESP during periods SF1/SF2 or SF3/SF4).
However, Choi, Kuang and Park do not appear to expressly disclose a temperature sensor configured to sense a temperature of the display device.
Jeon discloses a temperature sensor configured to sense a temperature of a display device (para[0027]; para[0036]; see in Figs. 1-2 sensor module 176 comprising a temperature sensor).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Choi’s, Kuang’s and Park’s combination, with the teachings in Jeon’s invention, to have a temperature sensor configured to sense a temperature of the display device, for the advantage of detecting and considering an operational state of the device to more efficiently compensate for a luminance difference in a first period (e.g., an address period) and/or a second period (e.g., a holding period) to control (e.g., decrease) a change in a screen (e.g., a flicker phenomenon) (para[0010]; para[0036]).
Regarding claim 20, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 15). In addition, Choi discloses changing a width of the first start signal or the second start signal (para[0012]; para[0048]; regarding Fig. 1, “the timing controller 140 may supply a plurality of emission start signals with different widths to the emission driver 130 in response to the control signal CS”, as shown in Fig. 8 for ESP during periods SF1/SF2 or SF3/SF4).
However, Choi, Kuang and Park do not appear to expressly disclose sensing a temperature of the display device; and changing a width of the first start signal or the second start signal based on the temperature.
Jeon discloses sensing a temperature of a display device (para[0027]; para[0036]; see in Figs. 1-2 sensor module 176 comprising a temperature sensor for sensing temperature of display device 101); and changing widths of signals based on the temperature (para[0010]; para[0029]; para[0036]; para[0109]; see in Figs. 1-2 and 11; “The auxiliary processor 123 may control at least some of functions or states related to at least one component (e.g., the display device 160, the sensor module 176, or the communication module 190) among the components of the electronic device 101…”; “The sensor module 176 may detect an operational state (e.g.,… temperature) of the electronic device 101…” and based on the state “the display driving circuit may compensate for a luminance difference in a first period (e.g., an address period) and/or a second period (e.g., a holding period) to control (e.g., decrease) a change in a screen (e.g., a flicker phenomenon)” by adjusting an emission signal (EM) width e.g. during the holding period).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Choi’s, Kuang’s and Park’s combination, with the teachings in Jeon’s invention, to have sensing a temperature of the display device; and changing a width of the first start signal or the second start signal based on the temperature, for the advantage of detecting and considering an operational state of the device to more efficiently compensate for a luminance difference in a first period (e.g., an address period) and/or a second period (e.g., a holding period) to control (e.g., decrease) a change in a screen (e.g., a flicker phenomenon) (para[0010]; para[0036]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2019/0057650), in view of Kuang et al. (US 2023/0419904) and Park et al. (US 2013/0286003), and further in view of In et al. (US 2021/0366408).
Regarding claim 9, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 1). However, Choi, Kuang and Park do not appear to expressly disclose the emission driver comprises the selector.
In discloses an emission driver comprising a selector that supplies a start signal (see emission driver 600 in Figs. 1 and 4 comprising stages ST, wherein “Each stage ST1 to STM outputs the emission signal EM and the emission signal EM is inputted to an input terminal of a next stage”, and “A start signal of the stage may be the emission signal EM of a previous stage”; accordingly, based on the broadest reasonable interpretation of the claimed limitations, internally, the emission driver comprises a selector that supplies start signals, as claimed).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Choi’s, Kuang’s and Park’s combination, with the teachings in In’s invention, to have the emission driver comprises the selector, for the advantage of a configuration that allows enhancing a display quality of a display panel by preventing an image flashing occurred at an initial driving period and an abnormal off situation (para[0005]).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2019/0057650), in view of Kuang et al. (US 2023/0419904) and Park et al. (US 2013/0286003), and further in view of Park et al. (US 2022/0366835), hereinafter Park ‘835, and Kim et al. (US 2020/0135091).
Regarding claim 10, Choi, Kuang and Park disclose all the claim limitations as applied above (see claim 1). In addition, Choi discloses a pixel among the pixels (e.g. pixel PXL in Figs. 1 and 3) comprises:
a light-emitting element for generating light corresponding to an amount of current flowing from a first power line, to which a first electrode is connected, to a second power line, to which a second electrode is connected (para[0012]; see light-emitting element OLED in Fig. 3 for emitting light in response to amounts of current that flow from a first driving power source ELVDD connected to the anode electrode of OLED, to a second driving power source ELVSS connected to the cathode electrode of OLED);
a first transistor connected between the first electrode of the light-emitting element and the first power line, and configured to control the amount of current corresponding to a voltage of a first node (para[0074]; see in Fig. 3 driver transistor MD connected between the anode electrode of the OLED and ELVDD, and configured to control current amount corresponding to a voltage of node N2);
a second transistor connected between one of the data lines and the first node, and comprising a gate electrode connected to a first scan line (see in Fig. 3 transistor M2 connected between a data line Dm and indirectly connected to node N2 through transistors MD and M4, with a gate electrode connected to scan line Si; para[0086]; para[0088]-para[0089]);
a third transistor connected between the first transistor and the first electrode of the light-emitting element, and comprising a gate electrode connected to a control line (see transistor M6 connected between driver transistor MD and the anode of the OLED, and comprising a gate electrode connected to emission control line Ei, as shown in Fig. 3);
a fourth transistor connected between the first electrode of the light-emitting element and a third power line to which an initialization power source is supplied, and comprising a gate electrode connected to the first scan line (see transistor M1 connected between the anode of the OLED and Vint, and comprising a gate electrode connected to Si, as shown in Fig. 3);
a sixth transistor connected between the first power line and the first transistor, and comprising a gate electrode connected to an emission control line (see transistor M5 connected between ELVDD and driver transistor MD, and comprising a gate electrode connected to emission control line Ei, as shown in Fig. 3); and
a second capacitor connected between the first power line and a second node as a common node between the first transistor and the third transistor (see capacitor Cst in Fig. 3 connected between ELVDD and a common node between driver transistor MD and transistor M6 through transistor M4).
In addition, Kuang discloses a fifth transistor connected between a fourth power line to which a reference power source is supplied and a first node, and comprising a gate electrode connected to a third scan line (see transistor M1 connected between Ref1 line to which a first reset signal is supplied and a first node N1, with a gate electrode connected to S1N, as shown in Fig. 2); wherein the fifth transistor comprises an N-type transistor (see M1 in Fig. 2 comprises an N-type transistor).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have a fifth transistor connected between a fourth power line to which a reference power source is supplied and the first node, and comprising a gate electrode connected to a third scan line, wherein the fifth transistor comprises an N-type transistor, for the advantage resetting the first node to eliminate an impact of a signal input to the first node N1 in a previous frame, while reducing an off-state leakage current of the fifth transistor, thus reducing the impact of the leakage current on the potential of the first node and improving the potential stability of the first node (para[0061]).
However, Choi, Kuang and Park do not appear to expressly disclose the third transistor comprising the gate electrode connected to a fourth scan line; the fourth transistor comprising the gate electrode connected to a second scan line; a first capacitor connected between the first node and the second node; and the first transistor, the second transistor, the third transistor, the fourth transistor, and the sixth transistor comprise N-type transistors.
Park ‘835 discloses a fourth transistor connected between a first electrode of a light-emitting element and a third power line to which an initialization power source is supplied, and comprising a gate electrode connected to a second scan line (see transistor T7 connected between an anode of light emitting element LD and a second initialization power source VINT2, with a gate electrode connected to scan signal GB[i], as shown in Fig. 3; para[0094]-para[0095]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Choi’s, Kuang’s and Park’s combination, with the teachings in Park ‘835’s invention, to have the fourth transistor comprising the gate electrode connected to a second scan line, for the advantage of independently discharging a parasitic capacitance which may occur in the light emitting element LD, so that the display quality of a black grayscale can be improved (para[0114]-para[0115]).
However, Choi, Kuang, Park and Park ’835 do not appear to expressly disclose the third transistor comprising the gate electrode connected to a fourth scan line; a first capacitor connected between the first node and the second node; and the first transistor, the second transistor, the third transistor, the fourth transistor, and the sixth transistor comprise N-type transistors.
Kim discloses a third transistor connected between a first transistor and the first electrode of the light-emitting element, and comprising a gate electrode connected to a fourth scan line (see in Fig. 8 transistor Tsw3 connected between driving transistor Tdr and the anode of light emitting device ELD, with a gate electrode connected to SPc supplied from gate line GLc; para[0132]); a first capacitor connected between a first node and a second node as a common node between the first transistor and the third transistor (see e.g. in Fig. capacitor C1 connected between a node at a gate of Tdr and a common/second node between Tdr and Tsw3); and all the transistors in the circuit comprise N-type transistors (see Fig. 8; para[0118]; para[0137]; para[0170]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Choi’s, Kuang’s, Park’s and Park ’835’s combination, with the teachings in Kim’s invention, to have the third transistor comprising the gate electrode connected to a fourth scan line; a first capacitor connected between the first node and the second node; and the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor comprise N-type transistors, for the advantage of having an internal compensation circuit capable of compensating a threshold voltage of a driving transistor without loss of a data voltage, and because it is conventional to alternatively use N-type transistors instead of P-type transistors with the appropriate control signals (para[0011]; para[0137]; para[0170]).
Regarding claim 11, Choi, Kuang, Park, Park ‘835 and Kim disclose all the claim limitations as applied above (see claim 10). In addition, Choi already discloses the first transistor comprises a first gate electrode connected to the first node (see in Fig. 3 the driver transistor MD comprising a first gate electrode connected to node N2).
In addition, Kim discloses a second gate electrode connected to the second node (see e.g. a second gate electrode of Tdr connected through C2 to the common/second node between Tdr and Tsw3, as shown in Fig. 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have a second gate electrode connected to the second node, as also taught by Kim, for the advantage of a pixel configuration that provides an internal compensation circuit capable of compensating a threshold voltage of a driving transistor without loss of a data voltage (para[0011]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Newly added limitations have now been treated on the merits and the above rejection has been modified in the same fashion as the amended claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GLORYVID FIGUEROA-GIBSON whose telephone number is (571)272-5506. The examiner can normally be reached on 9am-5pm, Monday -Friday, Eastern Time.
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628