DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 25, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because of the following reasons:
Regarding FIG. 2: S104 should be changed to “read a selected word line, and apply a first read bias set to unselected word lines”. S106 should be changed to “read the selected word line, and apply a second read bias set and a third read bias set to unselected word lines in a written area and an unwritten area, respectively”. Also see reasons explained in the objections to the specification.
Regarding FIG. 6: S204 should be changed to “apply a first word line read pass voltage to unselected word lines and apply a bit line read voltage to a bit line”. S208 should be changed to “apply a second read pass voltage and a third word line read pass voltage to unselected word lines in a written area and an unwritten area, respectively, and apply a bit line read voltage VBL_1 to corresponding bit lines when reading a selected word line”. S212 should be changed to “apply a second read pass voltage and a third word line read pass voltage to unselected word lines in a written area and unwritten area, respectively, and apply a bit line read voltage VBL_2 to corresponding bit lines when reading a select word line”. S218 should read “apply a first word line read pass voltage to unselected word lines and a bit line read voltage to bit lines in the block when reading a selected word line”. S216 should read “apply a second and a third word line read pass voltage to unselected word lines in a written area and an unwritten area, respectively, and apply a bit line read voltage VBL_N to corresponding bit lines when reading a selected word line”. Also see reasons explained in the objections to the specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
It seems that voltages applied to a bit line or bit lines got mis-labeled or confused with “pass voltages”, which are voltages applied to unselected word lines in a NAND memory during a program or read operation so that unselected transistors within a selected NAND string are turned on, regardless of whether they have been programmed or not, to pass current in a channel of a NAND string between a bit line and a source line. Pass voltages are not known in the art to be applied to bit lines. Examiner suggests to remove “pass” from the name of each bias set and remove “pass” from any voltage applied to a bit line.
Accordingly, it is suggested to amend the specification as follows:
[0004] As described above, the verification pass voltage Vpass_pv used during programming and the first word line read pass voltage Vpass_rd used during reading are different. In other words, the bias settings of the pass voltages for the word lines word lines/bit lines used during programming and reading are different. However, applying too large voltage may change the threshold voltage of the memory cell.
[0009] Based on the above, when the open block of the flash memory is read, the word line read pass voltage applied to the unselected word lines in the unwritten area is set to be different from the word line read pass voltage applied to the unselected word lines in the written area, to reduce false readings and read interference. In addition, according to the position of the final written word line, the bit line read pass voltage of the bit line may be adjusted accordingly, which may further reduce misreading and read interference.
[0023] Next, in step S102, when it is determined that the block to be read is a non-open block 100A as shown in FIG. 3A, step S104 is executed. In step S104, all the memory cells in the block have been programmed, so the current read method may be adopted to read the selected word line WLj. Specifically, a word line read voltage V_rd is applied to the selected word line WLj and an appropriate bit line read voltage Vbl is applied to the selected bit line to perform reading. At the same time, a first read pass bias set is applied to the unselected word lines WL1 to WLj-1 and WLj+1 to WLn in the block 100A. The first read pass bias set includes a first word line read pass voltage Vpass_rd and a first bit line read pass voltage Vblc_rd, as shown in FIG. 3A. In this way, memory cells on unselected word lines are turned on.
[0026] As shown in FIG. 3B, a second read pass bias set is applied to the unselected word lines WL1 to WLj-1 and WLj+1 to WLPA in the written area 102 of the open block 100. According to an embodiment of the invention, the second read pass bias set may include a second word line read pass voltage Vpass_x and a second bit line read pass voltage Vblc_xx. In addition, a third read pass bias set is applied to the unselected word lines WLPA+1 to WLn in the unwritten area 104 of the block 100. Here, the third read pass bias set may include a third word line read pass voltage Vpass_z and the second bit line read pass voltage Vblc_xx.
[0027] According to an embodiment of the invention, the third word line read pass voltage Vpass_z of the third read pass bias set is different from the second word line read pass voltage Vpass_x of the second read pass bias set. As an example, since the memory cells in the unwritten area 104 are all in a low-threshold voltage state, the third word line read pass voltage Vpass_z applied to the unselected word lines WLPA+1 to WLn may be set to be less than the second word line read pass voltage Vpass_x applied to the unselected word lines WL1 to WLj-1 and WLj+1 to WLPA.
[0028] Furthermore, in the above example, when the selected word line WLj is read, the same second read pass bias set is applied to the unselected word lines WL1 to WLj-1 and WLj+1 to WLPA in the written area 102 of the open block 100, but the invention is not limited thereto. As one example, the word line read pass voltage applied to the unselected word lines WL1 to WLj-1 and WLj+1 to WLPA in the written area 102 may be appropriately adjusted according to the position (number) of the word lines. For example, in the example of FIG. 3B, the word line read pass voltage Vpass_x may be applied to the unselected word lines WL1 to WLj-1, but the word line read pass voltage Vpass_y may be applied to the unselected word lines WLj+1 to WLPA. In addition, in this example, the unselected word lines WL1 to WLj-1 and WLj+1 to WLPA in the written area 102 are all divided into two sections, and different word line read pass voltages Vpass_x and Vpass_y are applied thereto respectively. However, the unselected word lines WL1 to WLj-1 and WLj+1 to WLPA may also be further divided into more sections to apply different word line read pass voltages.
[0029] Furthermore, according to an embodiment of the invention, the second word line read pass voltage Vpass_x (and/or Vpass_y) of the second read pass bias set applied to the unselected word lines WL1 to WLj-1 and WLj+1 to WLPA in the written area 102 may adopt the first word line read pass voltage Vpass_rd in the same manner as in the current method. Of course, the second word line read pass voltage Vpass_x (and/or Vpass_y) may also be set to be different from the first word line read pass voltage Vpass_rd.
[0039] FIG. 6 is a flowchart of determining a bit line read pass voltage according to an embodiment of the invention. FIG. 7 is a schematic block diagram of determining a bit line read pass voltage according to an embodiment of the invention. As shown in FIG. 7, the configuration example of the open block 100 here is the same as that of the above FIG. 3B, so the same portions are as provided in the above description, and repeated portions are omitted here. Here, the open block 100 may be further divided into a plurality of sections, such as section 1, section 2, ..., section N, wherein N is an integer. In addition, the final written word line address PA may be any area of the located in section 1, section 2, ..., section N. When reading the selected word line WLj, the word line read voltage V_rd is applied to the selected word line WLj, the second word line read pass voltage Vpass_x (and/or Vpass_y, as detailed above) is applied to the unselected word lines WL1 to WLj-1 and WLj+1 to WLPA of the written area 102, and the third word line read pass voltage Vpass_z is applied to the unselected word lines WLPA+1 to WLn of the unwritten area 104.
[0040] Any one of the bit line read pass voltages VBLx (x=1 to N, N is an integer) is applied to the bit lines of the corresponding unselected word lines WL1 to WLj-1, WLj+1 to WLPA, and WLPA+1 to WLn. That is, the bit line read pass voltage VBLx is determined according to which section of the sections 1 to N the final written word line WLPA is located in. Detailed description is given below with reference to FIG. 6.
[0042] Next, in step S202, when it is determined that the block to be read is not an open block, step S204 is executed. In step S204, the word line read voltage V_rd is applied to the selected word line WLj and the appropriate bit line read voltage Vbl is applied to the selected bit line to perform reading. At the same time, a first read pass bias set is applied to the unselected word lines WL1 to WLj-1 and WLj+1 to WLn in the block, and the first read pass bias set includes the first word line read pass voltage Vpass_rd and the first bit line read pass voltage Vblc_rd.
[0043] In addition, in step S202, when it is determined that the block to be read is the open block 100, step S206 is executed to further determine whether the final written word line WLPA is in the section 1. If the final written word line WLPA is in the section 1, step S208 is executed. In step S208, when the selected word line WLj is read, the second word line read pass voltage Vpass_x (and/or Vpass_y) is applied to the unselected word lines WL1 to WLj-1 and WLj+1 to WLPA of the written area 102, and the third word line read pass voltage Vpass_z is applied to the unselected word lines WLPA+1 to WLn of the unwritten area 104. In addition, a bit line read pass voltage VBL_1 is applied to the bit lines corresponding to the unselected word lines.
[0044] In step S206, if it is determined that the final written word line WLPA is not in the section 1, step S210 is executed. In step S210, it is further determined whether the final written word line WLPA is in the section 2. If the final written word line WLPA is in the section 2, step S212 is executed. In step S212, when the selected word line WLj is read, the second word line read pass voltage Vpass_x (and/or Vpass_y) is applied to the unselected word lines WL1 to WLj-1 and WLj+1 to WLPA of the written area 102, and the third word line read pass voltage Vpass_z is applied to the unselected word lines WLPA+1 to WLn of the unwritten area 104. In addition, a bit line read pass voltage VBL_2 is applied to the bit lines corresponding to the unselected word lines.
[0046] In step S214, if it is determined that the final written word line WLPA is not in the section N, step S218 is executed. In step S218, when the selected word line WLj is read, the first word line read pass voltage Vpass_rd and the first bit line read pass voltage Vblc_rd are is applied to the unselected word lines WL1 to WLj-1 and WLj+1 to WLn in the block.
[0047] When the open block is read, since the resistance of the memory cells in the low-threshold voltage state of the unwritten area 104 is different from the resistance of the memory cells in the high-threshold voltage state, the amount of memory cells in the low-threshold voltage state of the unwritten area 104 may be further determined by the final written word line address PA. Therefore, the bit line read pass voltage VBL_N applied to the bit line may be further adjusted correspondingly according to which section the final written word line WLPA is located in. Thereby, misreading and read interference may be further reduced.
[0048] Based on the above, when the open block of the flash memory is read, the word line read pass voltage applied to the unselected word lines in the unwritten area is set to be different from the word line read pass voltage applied to the unselected word lines in the written area, so as to reduce misreading and read interference. In addition, according to the position of the final written word line, the bit line read pass voltage of the bit line may be adjusted accordingly, which may further reduce misreading and read interference.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 14-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because these claims are claiming a command format, which is just an order of data.
Guidance to consider of how to possibly overcome the 101 rejection is as follows:
Claim 14: A flash memory device being responsive to a command having a A read command format for a flash memory device, comprising:
a special code, used to specify whether each of a plurality of blocks in the flash memory device is an open block;
a final written word line address, used to specify an address of a final written word line in each of the plurality of blocks; and
a read command specification in compliance with a standard format of the flash memory device, wherein and the read command specification further comprises, in sequence, a read command code, a column address, a row address, and a read confirmation command sequentially.
Claim 15: The read command format for the flash memory device of claim 14, wherein the special code and the final written word line address are arranged added before the read command specification.
Claim 16: The read command format for the flash memory device of claim 14, wherein the special code is arranged before the read command code of the read command specification, and the column address is replaced by the final written word line address.
Claim 17: The read command format for the flash memory device of claim 14, wherein the read command format further comprises a first portion and a second portion, the first portion comprises a prefix, the read command code, the column address, the final written word line address, and the special code in sequence, and the second portion is the read command specification.
Claim 18: The read command format for the flash memory device of claim 14, wherein the read command format further comprises a set feature value portion, the set feature value portion comprises a set feature command, a feature value, and the final written word line address in sequence.
Claim 19: The read command format for the flash memory device of claim 14, wherein the read command format further comprises comprising a prefix arranged before the special code.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION-The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-5, 9-12, and 16-17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2: It is unknown what is meant by “bit line read pass voltage”. Such a term is not standard in the art. There is a word line pass voltage that is used in the art of NAND flash memory but NOT a bit line pass voltage. Claim 4 depends on claim 2.
Regarding claim 3: It is unknown what is meant by “bit line read pass voltage”. Such a term is not standard in the art. There is a word line pass voltage that is used in the art of NAND flash memory but NOT a bit line pass voltage.
Regarding claim 5: It is unknown what is meant by “bit line read pass voltage”. Such a term is not standard in the art. There is a word line pass voltage that is used in the art of NAND flash memory but NOT a bit line pass voltage.
Regarding claim 6: Since claim 1 already claimed a read command is appended with a special code and a final written word line address then it is unknown and indefinite how the read command format of the read command would include the special code and the final written word line address.
Regarding claim 9: Claim 6 already stated “the read command specification comprises a read command code, a column address, a row address, and a read confirmation command in sequence” so now stating “the final written word line address replaces the column address” is conflicting and, therefore, indefinite. The claim is improper because it fails to include all the limitations of the claim it depends on since it attempts to modify subject matter of a claim on which it depends instead of further narrowing the subject matter of the claim on which it depends.
Regarding claim 10: Claim 6 already stated “the read command format is a read command specification plus the special code and the final written word line address” so now stating “the read command format further comprises a prefix arranged before the special code” is conflicting and, therefore, indefinite. The claim is improper because it fails to include all the limitations of the claim it depends on since it attempts to modify subject matter of a claim on which it depends instead of further narrowing the subject matter of the claim on which it depends.
Regarding claim 11: In plain English portions of a whole must not overlap since they are separate portions or pieces of a whole.
Claim 1 claims a read command that is appended with a special code and a final written word line address.
Claim 11 then claims that the read command comprises a first portion and a second portion.
It is unknown, and therefore indefinite, how a first portion of the read command could also comprise the final written word line address, which was already claimed in claim 1 to be a separate entity appended to the read command. Likewise, it is unknown, and therefore indefinite, how the first portion of the read command could also comprise the special code, which was also already claimed in claim 1 to be another separate entity appended to the read command and the final written word line address.
Also, each of the limitations “the read command code” and “the column address” lacks sufficient antecedent basis.
Regarding claim 12: In plain English portions of a whole must not overlap since they are separate portions or pieces of a whole.
Claim 1 claims a read command that is appended with a special code and a final written word line address.
Claim 12 then claims that the read command comprises a set feature value portion and a read command specification.
It is unknown, and therefore indefinite, how a portion of the read command could also comprise the final written word line address, which was already claimed in claim 1 to be a separate entity appended to the read command.
Likewise, it is unknown, and therefore indefinite, how the rad command specification within the read command could also comprise the special code, which was also already claimed in claim 1 to be another separate entity appended to the read command and the final written word line address.
Regarding claim 16: Stating “the column address is replaced by the final written word line address” is conflicting and, therefore, indefinite. The claim is improper because it fails to include all the limitations of the claim it depends on since it attempts to modify subject matter of a claim on which it depends instead of further narrowing the subject matter of the claim on which it depends. It simply makes no sense replacing the column address of the read command specification with the final written word line address, which is another element of the read command outside of the read command specification as already claimed in claim 14.
Regarding claim 17: Claim 14 already has claimed the read command code, the column address, the row address and the read confirmation command arranged in a sequence. So now claiming a prefix, the read command code, the column address, the final written word line address, and the special cod in sequence is conflicting and indefinite.
Allowable Subject Matter
Claims 1, 6-8, and 13 allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
Prosecution Insights