DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communication filed on 10/16/2024.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-3 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter, software per se. The claim does not fall within at least one of the four categories of patent eligible subject matter. Claim 1 recites a scrambler and a digital to analog converter which can be software (the specification does not limit these terms to be hardware only). As such, claim 1 does not fall within at least one of the four categories of patent eligible subject matter because the claim does not include at least one hardware element in the body of the claim as required by MPEP 2106(I). Claims 2 and 3 depend from claim 1 and are rejected under same rationale as they do not cure the deficiency of claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 8-10, 13, 15-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hustava et al. (US 2020/0153653).
Claim 1, Hustava teaches:
An integrated circuit comprising:
a scrambler configured to process data packets into masked data packets using a configuration or an initial state derived by proprietary processing of a seed value stored in the clear or received via a bus; and (e.g., fig. 2, [0028], “Various standards exist to support communications between the ECU 102 and the various sensors and actuators. Of particular interest with respect to the present disclosure is the 3rd generation Distributed System Interface (DSI3) bus standard, which provides for half-duplex single-ended signal communication between a bus master device (typically the ECU) and one or more slave devices (e.g., the sensors and actuators)” [0029], “slave device 200 suitable for use on a standard DSI3 bus” [0030], “Slave device 200 includes a controller 202 that collects measurements and buffers relevant messages in memory 204 for communicating the measurement data to the bus master device…A scrambler 206 masks each message with a pseudorandom binary sequence using a bitwise exclusive-or (XOR) operation to randomize or "whiten" any repeating data patterns…The seed for the pseudorandom sequence may vary for each message and may vary for each slave device”)
a digital-to-analog converter configured to send the masked data packets via the bus. (e.g., figs. 1-2, [0008], “the signal conductor is a Distributed System Interface (DSI) coupling an automotive sensor to an electronic control unit (ECU)” [0027], “FIG. 1 shows an electronic control unit (ECU) 102 coupled to the various ultrasonic sensors 104 and a radar array controller 106 as the center of a star topology” [0028], “Various standards exist to support communications between the ECU 102 and the various sensors and actuators. Of particular interest with respect to the present disclosure is the 3rd generation Distributed System Interface (DSI3) bus standard, which provides for half-duplex single-ended signal communication between a bus master device (typically the ECU) and one or more slave devices (e.g., the sensors and actuators)” [0029], “slave device 200 suitable for use on a standard DSI3 bus” [0030], “Slave device 200 includes a controller 202 that collects measurements and buffers relevant messages in memory 204 for communicating the measurement data to the bus master device…A scrambler 206 masks each message with a pseudorandom binary sequence using a bitwise exclusive-or (XOR) operation to randomize or "whiten" any repeating data patterns” [0032], “A digital-to-analog converter 212 operates on the filtered channel signal to convert it from digital form to analog form, which herein may be termed the uplink channel signal” [0038], “FIG. 2B is a block diagram of an illustrative bus master device 240 suitable for use on a standard DSI3 bus. As with the slave device 200, the master device 240 maintains physical compatibility with the DSI3 standard, but includes certain features to enhance uplink communication performance when employed in conjunction with a compatible slave device”)
Claim 2, Hustava teaches:
wherein the scrambler processes data packets without being reset between transmissions. (e.g., [0028], [0030], [0050])
Claim 3, Hustava teaches:
a descrambler configured to receive and unmask command messages from a bus controller device using the configuration or the initial state derived by proprietary processing of the seed value. (e.g., [0041])
Claim 6, Hustava teaches:
an integrated circuit component configured to derive the configuration or the initial state using a digital filter. (e.g., fig. 2, [0030])
Claim 8, Hustava teaches:
A bus communication method comprising:
using a scrambler to process data packets into masked data packets using a configuration or an initial state derived by proprietary processing of a seed value stored in the clear or received via a bus; and (e.g., fig. 2, [0028], “Various standards exist to support communications between the ECU 102 and the various sensors and actuators. Of particular interest with respect to the present disclosure is the 3rd generation Distributed System Interface (DSI3) bus standard, which provides for half-duplex single-ended signal communication between a bus master device (typically the ECU) and one or more slave devices (e.g., the sensors and actuators)” [0029], “slave device 200 suitable for use on a standard DSI3 bus” [0030], “Slave device 200 includes a controller 202 that collects measurements and buffers relevant messages in memory 204 for communicating the measurement data to the bus master device…A scrambler 206 masks each message with a pseudorandom binary sequence using a bitwise exclusive-or (XOR) operation to randomize or "whiten" any repeating data patterns…The seed for the pseudorandom sequence may vary for each message and may vary for each slave device”)sending the masked data packets via the bus. (e.g., figs. 1-2, [0008], “the signal conductor is a Distributed System Interface (DSI) coupling an automotive sensor to an electronic control unit (ECU)” [0027], “FIG. 1 shows an electronic control unit (ECU) 102 coupled to the various ultrasonic sensors 104 and a radar array controller 106 as the center of a star topology” [0028], “Various standards exist to support communications between the ECU 102 and the various sensors and actuators. Of particular interest with respect to the present disclosure is the 3rd generation Distributed System Interface (DSI3) bus standard, which provides for half-duplex single-ended signal communication between a bus master device (typically the ECU) and one or more slave devices (e.g., the sensors and actuators)” [0029], “slave device 200 suitable for use on a standard DSI3 bus” [0030], “Slave device 200 includes a controller 202 that collects measurements and buffers relevant messages in memory 204 for communicating the measurement data to the bus master device…A scrambler 206 masks each message with a pseudorandom binary sequence using a bitwise exclusive-or (XOR) operation to randomize or "whiten" any repeating data patterns” [0038], “FIG. 2B is a block diagram of an illustrative bus master device 240 suitable for use on a standard DSI3 bus. As with the slave device 200, the master device 240 maintains physical compatibility with the DSI3 standard, but includes certain features to enhance uplink communication performance when employed in conjunction with a compatible slave device”)
Claim 9, this claim is directed to a method containing similar limitations as recited in claim 2 and is rejected for similar rationale.
Claim 10, this claim is directed to a method containing similar limitations as recited in claim 3 and is rejected for similar rationale.
Claim 13, this claim is directed to a method containing similar limitations as recited in claim 6 and is rejected for similar rationale.
Claim 15, Hustava teaches:
A bus controller comprising:
an integrated circuit component configured to perform proprietary processing of multiple seed values, each of the multiple seed values being associated with a respective slave device, the proprietary processing producing a scrambler configuration or an initial scrambler state for the respective slave device; and (e.g., figs. 1-2, [0027], “FIG. 1 shows an electronic control unit (ECU) 102 coupled to the various ultrasonic sensors 104 and a radar array controller 106 as the center of a star topology” [0028], “the 3rd generation Distributed System Interface (DSI3) bus standard, which provides for half-duplex single-ended signal communication between a bus master device (typically the ECU) and one or more slave devices (e.g., the sensors and actuators)” [0030], “Slave device 200 includes a controller 202 that collects measurements and buffers relevant messages in memory 204 for communicating the measurement data to the bus master device…A scrambler 206 masks each message with a pseudorandom binary sequence using a bitwise exclusive-or (XOR) operation to randomize or "whiten" any repeating data patterns…The seed for the pseudorandom sequence may vary for each message and may vary for each slave device”)
a descrambler configured to use the scrambler configuration or the initial scrambler state for each respective slave device to unmask masked data packets received from that respective slave device. (e.g., [0041], “A descrambler 257 operates on the bitstream from the decoder 256, inverting the operation of the scrambler 206 to extract the message data sent by the slave device. The message data may be stored in memory 244 for analysis and use by controller 242”)
Claim 16, Hustava teaches:
a scrambler configured to use the scrambler configuration or the initial scrambler state for each respective slave device to process message packets into masked message packets for that respective slave device; and a digital-to-analog converter configured to send the masked message packets via the bus. (e.g., figs. 1-2, [0028]-[0030], [0032])
Claim 17, Hustava teaches:
a memory configured to preserve a current scrambler state for each respective slave device between reception of masked data packets from that respective slave device. (e.g., figs. 1-2, [0030], [0039], [0041])
Claim 20, this claim is directed to a bus controller containing similar limitations as recited in claim 6 and is rejected for similar rationale.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5, 11-12, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hustava et al. (US 2020/0153653) in view of Butler (US 6,678,707).
Claim 4, Hustava teaches an integrated circuit component configured to derive the configuration or the initial state (e.g., figs. 1-2, [0030]) and does not appear to explicitly teach but Butler teaches:
using built-in self-test (BIST) circuitry. (e.g., col. 4 ll. 44-48, col. 5 ll. 28-32, col. 9 ll. 24-28)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings described by Butler into the invention of Hustava, and the motivation for such an implementation would be for the purpose of providing a random number generation at no additional cost and insuring testability (Butler col. 5 ll. 30-32).
Claim 5, Hustava-Butler teaches:
wherein the BIST circuitry is configured to provide the configuration or initial state as a test result. (e.g., Hustava [0030]; Butler col. 4 ll. 44-48, col. 5 ll. 28-32, col. 9 ll. 24-28)
Same motivation as presented in claim 4 would apply.
Claim 11, this claim is directed to a method containing similar limitations as recited in claim 4 and is rejected using the same rationale to combine the references.
Claim 12, this claim is directed to a method containing similar limitations as recited in claim 5 and is rejected using the same rationale to combine the references.
Claim 18, this claim is directed to bus controller containing similar limitations as recited in claim 4 and is rejected using the same rationale to combine the references.
Claim 19, this claim is directed to bus controller containing similar limitations as recited in claim 5 and is rejected using the same rationale to combine the references.
Claims 7, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hustava et al. (US 2020/0153653) in view of Evans (US 2007/0291933).
Claim 7, Hustava teaches the digital filter, the seed value, the configuration or the initial state (see above) and does not appear to explicitly teach but Evans teaches:
produce truncated bits while operating on a seed value, and wherein a configuration or an initial state is derived using the truncated bits. (e.g., [0013]-[0017])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings described by Evans into the invention of Hustava, and the motivation for such an implementation would be for the purpose of securing a message transmitted between two devices (Evans [0017]).
Claim 14, this claim is directed to a method containing similar limitations as recited in claim 7 and is rejected using the same rationale to combine the references.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2016/0188523 discloses a system that supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMIE C LIN whose telephone number is (571)272-7752. The examiner can normally be reached M-F 9:00AM -5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GELAGAY SHEWAYE can be reached at (571)272-4219. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMIE C. LIN/Primary Examiner, Art Unit 2436
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