DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in reply to an amendment filed on January 29, 2026 regarding Application No. 18/917,642. Applicants amended claims 1, 5-6, 10, 12-14, 16, and 20. Claims 1-20 are pending.
Priority
Acknowledgment is made of Applicants’ claim for foreign priority under 35 U.S.C. 119(a)-(d). A certified copy of the KR 10-2024-0030803 application filed in Korea on March 4, 2024 has been filed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 3, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Office.
Response to Arguments
Applicants’ amendment to the specification and remarks (Remarks/Arguments, p. 12) regarding objection to the specification are acknowledged. In view of the amendment, the objection is moot.
Applicants’ amendments to the drawings and remarks (Remarks/Arguments, p. 12) regarding objections to the drawings are acknowledged. In view of the corrected drawings, the objections are moot.
Applicants’ amendments to claims 5-6, 10, and 12-14 and remarks (Remarks/Arguments, pp. 12-13) regarding objections to the claims are acknowledged. In view of the amendments, the objections are moot.
Applicants’ arguments filed on January 29, 2026 have been fully considered but they are moot in view of new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicants are advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kondo et al. in US 6,633,134 B1 (hereinafter Kondo) in view of Newell et al. in US 9,829,710 B2 (hereinafter Newell), in further view of Kozuma et al. in US 2024/0090284 A1 (hereinafter Kozuma).
Note: In the discussion below, pixels corresponding to the array of dotted outline squares in FIG. 7 of Kondo are identified by (row, column) coordinates where rows 1 and 6 are the top and bottom rows and columns 1 and 6 are the left and right columns, respectively (e.g., (1, 1) corresponds to the top row, left column and (6, 6) corresponds to the bottom row, right column, and, e.g., (1 to 3, 2 to 4) corresponds to rows 1-3, columns 2-4 ((1, 2), (1, 3), (1, 4), (2, 2), (2, 3), (2, 4), (3, 2), (3, 3), and (3, 4))).
Regarding claim 1, Kondo teaches:
A display device (see FIG. 5) comprising (Kondo: FIG. 5 and col. 3, l. 7 (“FIG. 5 is a sectional view of an organic EL display device….”)):
a first single crystal semiconductor substrate (21 in FIG. 5) on which a plurality of pixel circuits (55 in FIG. 10) arranged along a first direction (horizontal direction) and a second direction (vertical direction) intersecting the first direction is located, the plurality of pixel circuits comprising a first transistor (57 in FIG. 10) (Kondo: see FIGs. 5-6 and 10, col. 3, ll. 9-10 (“FIG. 6 is a top plan view of the first layer in the multilayer substrate shown in FIG. 5.”), col. 5, ll. 21-22 (“… [T]he drive IC 21 including a pixel circuits 55 is fabricated on a silicon substrate….”) and ll. 31-33 (“… [T]he… second MOSFET[]… 57… can be formed on a single-crystalline silicon substrate….”), see also claims 1 and 5 (drive circuit including pixel circuits mounted on a silicon substrate));
a second substrate (11 in FIG. 5) on the first single crystal semiconductor substrate, the second substrate on which a plurality of pixels comprising a plurality of light emitting elements and arranged along the first direction and the second direction is located (Kondo: see FIGs. 5-6, col. 3, ll. 35-38 (“Referring to FIG. 5, the organic EL display device… includes a multilayer ceramic substrate 10, on which three pixel EL elements 41 of respective unit pixels are exemplarily depicted….”), and col. 4, ll. 10-13 (“In FIG. 6 wherein the first ceramic layer 11 is depicted by removing the anode 14 and the organic thin film 13, the cathode pattern includes a plurality of cathodes 12 arrayed in a matrix for defining a plurality of pixel areas….”)); and
a connection line layer (20, 22, and 15 in FIG. 5) between the plurality of light emitting elements and the first single crystal semiconductor substrate and comprising a plurality of bridge lines (15 in FIG. 5), each of the plurality of bridge lines electrically connected to one of the plurality of pixel circuits and one of the plurality of pixels (Kondo: FIGs. 5-8 and 10, col. 3, ll. 53-59 (“The cathodes 12 and the common anode 14 are connected to rear terminals 16 to 19, which are disposed on the rear surface of the multilayer substrate 10, through interconnects 15 and via holes formed in the multilayer substrate 10. The rear terminals 16 to 19 are connected to respective pads of a drive IC 21 by metallic bumps 24. The drive IC 21 is mounted on the second substrate 500 which is mounted to the rear surface of the substrate 40….”), and col. 4, ll. 6-9 (“[T]he multilayer substrate 10… includ[es] second (intermediate) ceramic layer 22 and third (rear) ceramic layer 20 shown in FIGs…. [7] to 8, respectively.”) and ll. 46 and 49-51 (“Referring to FIG. 10, the drive IC 21 includes… a plurality of pixel circuits 55 each disposed for a corresponding one of pixel EL elements 41….”), see also col. 4, ll. 14-16 (“… Each cathode 12 [in FIG. 6] is connected to a corresponding rear terminal on the rear side of the multilayer substrate 10 through a via hole (not shown) formed in the first layer 11. ”), ll. 21-24 (“In FIG. 7, the second ceramic layer 22 mounts thereon interconnects 15, each of which extends on the second ceramic layer 22 and connects a via hole formed in the first layer 11 for a corresponding cathode 12 to a corresponding via hole formed in the second ceramic layer 22….”) and ll. 26-31 (“In FIG. 8, the third ceramic layer 20 mounts interconnects (not shown) at the front surface thereof and mounts the drive IC 21 at the rear surface thereof. Via holes 32 are formed in the third layer 20 for the respective cathodes 12 in the pixel EL elements 41….”) and col. 5, ll. 21-24 (“… [T]he drive IC 21 including a pixel circuits 55 is fabricated on a silicon substrate separately from the pixel EL elements 41 which are formed on the multilayer substrate 10….”)),
wherein the second substrate includes a plurality of through holes in which a corresponding ones of conductive vias electrically connected to corresponding ones of the plurality of light emitting elements of each of the plurality of sub-pixels and corresponding ones of the plurality of bridge lines is located (Kondo: see FIGs. 5-6 and 10, col. 3, ll. 53-59 (“The cathodes 12 and the common anode 14 are connected to rear terminals 16 to 19, which are disposed on the rear surface of the multilayer substrate 10, through interconnects 15 and via holes formed in the multilayer substrate 10. The rear terminals 16 to 19 are connected to respective pads of a drive IC 21 by metallic bumps 24. The drive IC 21 is mounted on the second substrate 500 which is mounted to the rear surface of the substrate 40….”), and col. 4, ll. 14-16 (“In FIG. 6 wherein the first ceramic layer 11 is depicted by removing the anode 14 and the organic thin film 13, the cathode pattern includes a plurality of cathodes 12 arrayed in a matrix for defining a plurality of pixel areas. Each cathode 12 is connected to a corresponding rear terminal on the rear side of the multilayer substrate 10 through a via hole (not shown) formed in the first layer 11. A pad section 35 disposed for the anode 14 has a rectangular shape, and is connected to the rear terminal through a plurality of via holes formed in the multilayer substrate 10.”) and ll. 46 and 49-51 (“Referring to FIG. 10, the drive IC 21 includes… a plurality of pixel circuits 55 each disposed for a corresponding one of pixel EL elements 41….”), see also FIGs. 7-8, col. 4, ll. 14-16 (“… Each cathode 12 [in FIG. 6] is connected to a corresponding rear terminal on the rear side of the multilayer substrate 10 through a via hole (not shown) formed in the first layer 11. ”), ll. 21-24 (“In FIG. 7, the second ceramic layer 22 mounts thereon interconnects 15, each of which extends on the second ceramic layer 22 and connects a via hole formed in the first layer 11 for a corresponding cathode 12 to a corresponding via hole formed in the second ceramic layer 22….”) and ll. 26-31 (“In FIG. 8, the third ceramic layer 20 mounts interconnects (not shown) at the front surface thereof and mounts the drive IC 21 at the rear surface thereof. Via holes 32 are formed in the third layer 20 for the respective cathodes 12 in the pixel EL elements 41….”) and col. 5, ll. 21-24 (“… [T]he drive IC 21 including a pixel circuits 55 is fabricated on a silicon substrate separately from the pixel EL elements 41 which are formed on the multilayer substrate 10….”)),
wherein the connection line layer comprises a first conductive layer (middle 15 layer in FIG. 5) at which a first bridge line is located, a second conductive layer (lower 15 layer in FIG. 5) at which a second bridge line is located, and an interlayer insulating layer (22 in FIG. 5) between the first conductive layer and the second conductive layer (Kondo: see FIGs. 5 and 7-8, col. 3, ll. 53-59 (“The cathodes 12 and the common anode 14 are connected to rear terminals 16 to 19, which are disposed on the rear surface of the multilayer substrate 10, through interconnects 15 and via holes formed in the multilayer substrate 10. The rear terminals 16 to 19 are connected to respective pads of a drive IC 21 by metallic bumps 24. The drive IC 21 is mounted on the second substrate 500 which is mounted to the rear surface of the substrate 40….”) and col. 4, ll. 20-25 (“In FIG. 7, the second ceramic layer 22 mounts thereon interconnects 15, each of which extends on the second ceramic layer 22 and connects a via hole formed in the first layer 11 for a corresponding cathode 12 to a corresponding via hole formed in the second ceramic layer 22. Other via holes 23 are disposed for the anode 14.”) and ll. 26-31 (“In FIG. 8, the third ceramic layer 20 mounts interconnects (not shown) at the front surface thereof and mounts the drive IC 21 at the rear surface thereof. Via holes 32 are formed in the third layer 20 for the respective cathodes 12 in the pixel EL elements 41….”),
wherein at least some of the plurality of pixels are electrically connected to the first bridge line, and other ones of the plurality of pixels adjacent to the sub-pixels connected to the first bridge line are electrically connected to the second bridge line (Kondo: i.e., where the first and second bridge lines each include a plurality of bridge lines in a same layer; see FIGs. 5-7.).
However, it is noted that Kondo does not teach:
said second substrate is a second single crystal semiconductor substrate, and
said plurality of pixels are a plurality of sub-pixels.
Newell teaches:
a second single crystal semiconductor substrate (408 in FIG. 4) on a first single crystal semiconductor substrate (428 in FIG. 4), the second single crystal semiconductor substrate on which a plurality of sub-pixels (414A-C in FIG. 4) comprising a plurality of light emitting elements and arranged along a first direction (horizontal direction) and a second direction (vertical direction) is located (Newell: FIGs. 2 and 4, col. 2, ll. 36-46 (“… [T]he display panel is produced by combining multiple separate stacked layers or components, such as to have one layer or component (referred to herein at times as an “emission layer” or “emission layer component”) with numerous pixels that emit light, and to have at least one other layer or component (referred to herein at times as a “control logic layer” or “control logic layer component”) that includes integrated circuits and/or pixel drivers or other logic to control and drive the emission of light by the pixels in the emission layer…. [T]he different layers are separate silicon chips or wafers….”) and col. 8, ll. 17-19 (“…. The display panel [200 in FIG. 2] includes a number of pixels 202 arranged in an array having M rows and N columns, where M and N may be the same or different….”) and ll. 48-60 (“The emission layer component 402 [of display panel 400 in FIG. 4] comprises a plurality of OLED pixels 406A-406C (collectively pixels 406) disposed on a top side 424 (as shown) of a silicon substrate 408… Each of the OLED pixels 406A-406C includes respective anode layers 410A-410C, a cathode layer 412 which may be common to the pixels, and respective emissive layers 414A-414C formed between the cathode layer and the anode layers. For explanatory purposes, FIG. 4 shows three subpixels, namely, a red subpixel 414A, a green subpixel 414B, and a blue subpixel 414C.”), and col. 9, ll. 19-23 (“The control logic layer component 404 comprises a substrate 428 (e.g., silicon,… etc.) which includes one or more control logic circuits thereon which drive or control the display of light by the plurality of pixels 406 on the interposer 408….”)), see also FIG. 3 (pixel 300 and sub-pixels 302A-C) and FIG. 6).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Newell, such that Kondo as modified teaches:
a second single crystal semiconductor substrate on the first single crystal semiconductor substrate, the second single crystal semiconductor substrate on which a plurality of sub-pixels comprising a plurality of light emitting elements and arranged along the first direction and the second direction is located (second substrate, first single crystal semiconductor substrate, plurality of pixels, plurality of light emitting elements, and first and second directions of Kondo combined with the first and second single crystal semiconductor substrates, plurality of sub-pixels, plurality of light emitting elements, and first and second directions of Newell); and a connection line layer between the plurality of light emitting elements and the first single crystal semiconductor substrate and comprising a plurality of bridge lines, each of the plurality of bridge lines electrically connected to one of the plurality of pixel circuits and one of the plurality of sub-pixels (connection line layer, plurality of light emitting elements, first single crystal semiconductor substrate, plurality of bridge lines, plurality of pixel circuits, and plurality of pixels of Kondo combined with the plurality of sub-pixels of Newell), wherein the second single crystal semiconductor substrate includes a plurality of through holes in which a corresponding ones of conductive vias electrically connected to corresponding ones of the plurality of light emitting elements of each of the plurality of sub-pixels and corresponding ones of the plurality of bridge lines is located (second substrate, plurality of through holes, conductive vias, plurality of light emitting elements, plurality of pixels, and plurality of bridge lines of Kondo combined with the second single crystal semiconductor substrate of Newell ), wherein at least some of the plurality of sub-pixels are electrically connected to the first bridge line, and other ones of the plurality of sub-pixels adjacent to the sub-pixels connected to the first bridge line are electrically connected to the second bridge line (some of the plurality of pixels, first and second bridge lines, and other ones of the plurality of pixels of Kondo combined with the plurality of sub-pixels of Newell), to “produce display panels [of head mounted displays] with sizes, pixel resolutions and other operational characteristics that enable a ‘retinal’ level of display, such that a wearer is unable to discern individual pixels at the distances and field of view for such a viewing experience in the head mounted display….” (Newell: col. 2, ll. 53-58, see also col. 7, ll. 2-14).
However, it is noted that Kondo as modified by Newell, as particularly cited, does not teach:
wherein a sub-pixel of the plurality of sub-pixels is connected to the first bridge line, the first bridge line being entirely spaced from a center of the sub-pixel in a direction crossing the first direction and the second direction on a plane parallel to the first single crystal semiconductor substrate.
Kozuma teaches:
wherein a sub-pixel (e.g., ARA [1,1] in FIG. 3A) of a plurality of sub-pixels (ARAs) is connected to a first bridge line (e.g., SL[1,1]_1), the first bridge line being entirely spaced from a center of the sub-pixel in a direction crossing a first direction (horizontal direction) and a second direction (vertical direction) on a plane parallel to a first single crystal semiconductor substrate (BS in FIG. 1) (Kozuma: see FIGs. 1, 2B, and 3A, “[0114] As the substrate BS [in FIG. 1], a semiconductor substrate (e.g., a single crystal substrate) formed of silicon or germanium can be used, for example….”, “[0122] The pixel layer PXAL includes, for example, a plurality of pixels. The plurality of pixels may be arranged in a matrix in the pixel layer PXAL.”, “[0123] Each of the plurality of pixels can express… a plurality of colors. In particular, the plurality of colors can be, for example, three colors of red (R), green (G), and blue (B)…. Note that in the case where each of pixels expressing different colors is called a subpixel and white is expressed by a plurality of subpixels expressing different colors, the plurality of subpixels are collectively called a pixel in some cases. In this specification and the like, a subpixel is referred to as a pixel for convenience.”, “[0133] As illustrated in FIG. 2B, for example, the local driver circuit LD[1,1] drives pixels included in the pixel region ARA[1,1]….”, “[0135]… As an example, a wiring group SLS[1,1] [in FIG. 3A] functions as a plurality of… wirings that electrically connect the plurality of pixels included in the pixel region ARA[1,1] and a… driver circuit included in the local driver circuit LD[1,1]….”, and “[0136] Consider a case where each of the pixel region ARA[1,1] to the pixel region ARA[m,n] includes a plurality of pixels arranged in a matrix of s rows and t columns (s is an integer of 1 or more and t is an integer of 1 or more) in FIG. 3A, as an example. In this case, for example,… the wiring group SLS[1,1]… has t… wirings. Note that in FIG. 3A,… a wiring SL[1,1]_1… [is] selectively illustrated as [a] wiring[] included in the wiring group SLS[1,1]...”, see also annotated FIG. 3A below and FIGs. 9A-B, 11-12, 16A, 26A).
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Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Kozuma, such that Kondo as modified teaches: wherein a sub-pixel of the plurality of sub-pixels is connected to the first bridge line, the first bridge line being entirely spaced from a center of the sub-pixel in a direction crossing the first direction and the second direction on a plane parallel to the first single crystal semiconductor substrate (plurality of sub-pixels, first bridge line, first and second directions, and first single crystal semiconductor substrate of Kondo as modified combined with the sub-pixel, plurality of sub-pixels, first bridge line, center of the sub-pixel, direction crossing first and second directions, and first single crystal semiconductor substrate of Kozuma), to connect a sub-pixel to a driving circuit as taught by Kozuma.
Regarding claim 2, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 1, wherein outermost sub-pixels in the first direction (e.g., (2,6) and (5,6) pixels in FIG. 7 of Kondo) and outermost sub-pixels in the second direction from among the plurality of sub-pixels are electrically connected to different first bridge lines (Kondo: outermost pixels in the first direction connected to different first bridges; see FIG. 7; claim 1 above (plurality of sub-pixels). It would have been obvious to one of ordinary skill in the art to include the claimed features to connect sub-pixels with pixel circuits.).
Regarding claim 3, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 2, wherein sub-pixels (e.g., (3 to 4, 1 to 5) pixels in FIG. 7 of Kondo) adjacent to inside of the outermost sub-pixels in the first and second directions from among the plurality of sub-pixels are electrically connected to different second bridge lines (Kondo: see FIG. 7; claim 1 above (plurality of sub-pixels) and claim 2 above).
Regarding claim 4, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 1, wherein a sub-pixel (e.g., (3, 6) pixel in FIG. 7 of Kondo) from among the plurality of sub-pixels of a first pixel row (e.g., row 3 in FIG. 7 of Kondo) located at one side (e.g., right side in FIG. 7 of Kondo) in the first direction is electrically connected to a pixel circuit from among the plurality of pixel circuits that is aligned in the first direction with the sub-pixel of the first pixel row, and a sub-pixel (e.g., (2, 6) pixel in FIG. 7 of Kondo) from among the plurality of sub-pixels of a second pixel row (e.g., row 2 in FIG. 7 of Kondo) adjacent to one side (e.g., upper side in FIG. 7 of Kondo) of the first pixel row in the second direction is electrically connected to a pixel circuit from among the plurality of pixel circuits that is not aligned in the first direction with the sub-pixel of the second pixel row (Kondo: see FIG. 7, see also FIG. 5; claim 1 above (plurality of sub-pixels)).
Regarding claim 5, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 4, wherein a bridge line of the plurality of bridge lines electrically connected to the sub-pixel of the first pixel row overlaps the sub-pixel of the first pixel row (Kondo: see FIG. 7, see also FIG. 5; claim 1 above (plurality of sub-pixels)).
Regarding claim 6, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 4, wherein at least a portion of a bridge line of the plurality of bridge lines electrically connected to the sub-pixel of the second pixel row overlaps the sub-pixel of the first pixel row (Kondo: see FIG. 7, see also FIG. 5; claim 1 above (plurality of sub-pixels)).
Regarding claim 7, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 4, wherein a first sub-pixel (e.g., (3, 6) pixel in FIG. 7 of Kondo) located at an outermost portion of the first pixel row is connected to the first bridge line, a second sub-pixel (e.g., (3, 5) pixel in FIG. 7 of Kondo) adjacent to the first sub-pixel of the first pixel row is connected to the second bridge line, and the first bridge line connected to the first sub-pixel is located on an other side (e.g., lower side in FIG. 7 of Kondo) of the second bridge line connected to the second sub-pixel in the second direction (Kondo: a first pixel located as claimed is connected to a bridge line, a second pixel as claimed, and the bridge line connected to the first pixel is located as claimed; see FIG. 7; claim 1 above (plurality of sub-pixels). It would have been obvious to one of ordinary skill in the art to include the claimed features to connect sub-pixels with pixel circuits.).
Regarding claim 8, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 4, wherein a sub-pixel (e.g., (6, 1) pixel in FIG. 7 of Kondo) from among the plurality of sub-pixels of a first pixel column (e.g., column 1 in FIG. 7 of Kondo) at an other side (e.g., lower side in FIG. 7 of Kondo) in the second direction is electrically connected to a pixel circuit from among the plurality of pixel circuits that is aligned in the second direction with the sub-pixel of the first pixel column, and a sub-pixel (e.g., (4, 2) pixel in FIG. 7 of Kondo) from among the plurality of sub-pixels of a second pixel column (e.g., column 2 in FIG. 7 of Kondo) adjacent to an other side (e.g., right side in FIG. 7 of Kondo) of the first pixel column in the first direction is electrically connected to a pixel circuit from among the plurality of pixel circuits that is not aligned in the second direction with the sub-pixel of the second pixel column (Kondo: see FIGs. 5 and 7; claim 1 above (plurality of sub-pixels)).
Regarding claim 9, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 8, wherein a first sub-pixel (e.g., (6, 1) pixel in FIG. 7 of Kondo) at an outermost portion of the first pixel column is connected to the first bridge line, a second sub-pixel (e.g., (5, 1) pixel in FIG. 7 of Kondo) adjacent to the first sub-pixel of the first pixel column is connected to the second bridge line, and the first bridge line connected to the first sub-pixel is located at one side (e.g., left side in FIG. 7 of Kondo) of the second bridge line connected to the second sub-pixel in the first direction (Kondo: a first pixel as claimed is connected to a bridge line, a second pixel as claimed is connected to the first bridge line, and the bridge line connected to the first pixel is located at one side of the first bridge line connected as claimed; see FIG. 7; claim 1 above (plurality of sub-pixels). It would have been obvious to one of ordinary skill in the art to include the claimed features to connect sub-pixels with pixel circuits.).
Regarding claim 10, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 1, wherein a first sub-pixel (e.g., (5, 1) pixel in FIG. 7 of Kondo) at an outermost portion from among the plurality of sub-pixels ((1, 5), (2, 4), (3, 3), (4, 2), and (5,1) pixels in FIG. 7 of Kondo) arranged along a diagonal direction is connected to the first bridge line, a second sub-pixel (e.g., (4, 2) pixel in FIG. 7 of Kondo) adjacent to the first sub-pixel in the diagonal direction is connected to the second bridge line, and the second bridge line is located above the first bridge line (Kondo: see FIGs. 5 and 7; claim 1 above (plurality of sub-pixels)).
Regarding claim 11, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 1, wherein a position of one end of the first bridge line in a sub-pixel (e.g., (2, 5) pixel in FIG. 7 of Kondo) from among the plurality of sub-pixels is different from a position of one end of the second bridge line in a sub-pixel (e.g., (3, 5) pixel in FIG. 7 of Kondo) adjacent to inside of the sub-pixel connected to the first bridge line (Kondo: see FIG. 7, see also FIG. 5; claim 1 above (plurality of sub-pixels)).
Regarding claim 12, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 1, wherein the plurality of sub-pixels comprises overlapping sub-pixels (e.g., (3 to 4, 1 to 6) pixels in FIG. 7 of Kondo) that overlap the pixel circuits, and non-overlapping sub-pixels (e.g., (1 and 6, 1 to 6) pixels in FIG. 7 of Kondo) that do not overlap the pixel circuits, and wherein a portion of a bridge line connected to a non-overlapping sub-pixel (e.g., (1, 1) pixel in FIG. 7 of Kondo) from among the plurality of bridge lines does not overlap the first single crystal semiconductor substrate (Kondo: see FIGs. 5 and 7-8; claim 1 above (plurality of sub-pixels)).
Regarding claim 13, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 12, wherein the bridge line connected to the non-overlapping sub-pixel from among the plurality of bridge lines is longer than a bridge line connected to an overlapping sub-pixel of the overlapping sub-pixels (e.g., (3, 1)) (Kondo: see FIGs. 5 and 7-8; claim 1 above (plurality of sub-pixels)).
Regarding claim 14, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 12, wherein a bridge line connected to an overlapping sub-pixel of the overlapping sub-pixels from among the plurality of bridge lines has a zigzag shape (It would have been obvious to one of ordinary skill in the art to include the claimed feature to connect a sub-pixel(s) to a pixel circuit(s)).
Regarding claim 15, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 1, wherein an area of the first single crystal semiconductor substrate is smaller than an area of the second single crystal semiconductor substrate (Kondo: FIGs. 5-8 and col. 4, ll. 31-34 (“… As depicted in FIG. 8, the drive IC 21 has planar dimensions significantly smaller than the planar dimensions of the multilayer substrate 10 mounting thereon the pixel EL elements 41.”); claim 1 above (second single crystal semiconductor substrate)).
Regarding claim 16, Kondo is modified in the same manner and for the same reasons set forth in the discussion of claim 1 above. Thus, claim 16 is rejected under similar rationale as claim 1 above.
However, it is noted that claim 16 differs from claim 1 above in that the following are recited:
a first single crystal semiconductor substrate on which a plurality of first transistors are located;
a plurality of conductive layers comprising a plurality of bridge contacts, and
wherein the plurality of sub-pixels comprises a first sub-pixel connected to one of the plurality of pixel circuits through a first bridge line at a first conductive layer of the connection line layer, and a second sub-pixel connected to one of the plurality of pixel circuits through a second bridge line at a second conductive layer on the first conductive layer of the connection line layer, and
wherein the first bridge line is entirely spaced from a center of the first sub-pixel in a direction on a plane parallel to the first single crystal semiconductor substrate.
Kondo as modified by Newell and Kozuma teaches:
a first single crystal semiconductor substrate on which a plurality of first transistors (57 in FIG. 10 of Kondo) and a plurality of pixel circuits are located, the plurality of pixel circuits comprising the first transistors (Kondo: FIGs. 5-6 and 10, col. 3, ll. 9-10 (“FIG. 6 is a top plan view of the first layer in the multilayer substrate shown in FIG. 5.”), col. 4, ll. 46 and 49-52 (“Referring to FIG. 10, the drive IC 21 includes… a plurality of pixel circuits 55 each disposed for a corresponding one of pixel EL elements 41 and including… a second MOSFET 57….”), col. 5, ll. 21-22 (“… [T]he drive IC 21 including a pixel circuits 55 is fabricated on a silicon substrate….”) and ll. 31-33 (“… [T]he… second MOSFET[]… 57… can be formed on a single-crystalline silicon substrate….”); claim 1 above);
wherein the connection line layer comprises a plurality of conductive layers comprising a plurality of bridge lines and a plurality of bridge contacts (corresponding to respectively electrically connected to the first and second bridge lines at the second and first conductive layers in FIG. 5 of Kondo), and an interlayer insulating layer between the plurality of conductive layers (Kondo: see FIG. 5; claim 1 above), and
wherein the plurality of sub-pixels comprises a first sub-pixel (a first pixel corresponding to middle 41 in FIG. 5 of Kondo) connected to one of the plurality of pixel circuits through a first bridge line at a first conductive layer (middle 15 layer in FIG. 5 of Kondo) of the connection line layer, and a second sub-pixel (a second pixel corresponding to right 41 in FIG. 5 of Kondo) connected to one of the plurality of pixel circuits through a second bridge line at a second conductive layer (lower 15 layer in FIG. 5 of Kondo) on the first conductive layer of the connection line layer (Kondo: see FIGs. 5-8; claim 1 above (including plurality of sub-pixels)), and
wherein the first bridge line is entirely spaced from a center of the first sub-pixel in a direction on a plane parallel to the first single crystal semiconductor substrate (first sub-pixel discussed above; claim 1 above).
Regarding claim 17, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 16, wherein the second bridge line is electrically connected to a first bridge contact at the first conductive layer, and the first bridge line is electrically connected to a second bridge contact at the second conductive layer (Kondo: see FIG. 5).
Regarding claim 18, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 17, wherein each of the second bridge line and the second bridge contact is connected to corresponding one of the conductive vias (Kondo: see FIG. 5).
Regarding claim 20, Kondo is modified in the same manner and for the same reasons set forth in the discussion of claim 1 above. Thus, claim 20 is rejected under similar rationale as claim 1 above.
However, it is noted that claim 20 differs from claim 1 above in that the following are recited:
A head mounted display device comprising:
a frame;
a plurality of display devices on the frame; and
lenses on each of the plurality of display devices.
Kondo as modified by Newell and Kozuma teaches:
A head mounted display device (100 in FIG. 1 of Newell) comprising (Newell: FIG. 1 and col. 7, ll. 56-58 (“FIG. 1 shows a simplified illustration of a head mounted display system 100 which is wearable on the head of a user for use in virtual reality and/or augmented reality situations and systems….”)):
a frame (102 in FIG. 1 of Newell) (Newell: FIG. 1 and col. 7, ll. 59-60 (“… The head mounted display system 100 includes a body 102 that supports two display panels 104A-104B….”));
a plurality of display devices (104A-B in FIG. 1 of Newell) on the frame (Newell: FIG. 1 and col. 7, ll. 59-62 (“… The head mounted display system 100 includes a body 102 that supports two display panels 104A-104B, each of which functions as the display for one eye of the user when the head mounted display system 100 is worn.”)); and
lenses on each of the plurality of display devices (Newell: FIGs. 1-3, col. 8, ll. 15-17 (“FIG. 2 shows a top view of example display panel 200, which may be similar or identical to each of the display panels 104A-104B of FIG. 1….”), ll. 26-28 (“FIG. 3 shows a top view of a pixel 300 which may be similar or identical to the pixels 202 of the display panel 200 of FIG. 2….”), and ll. 34-41 (“… The different colors for the subpixels 302A-302C may be produced by using direct emission (via different emission materials) or by using color filters, and using non-Lambertian emission to direct photons to the lens aperture, with a microlens (e.g., an aspheric Fresnel lens; SELFOC lens; graded-index, or GRIN, lens; etc.) optionally added for each of the subpixels 302A-302C.”), see also claim 7 (“The display panel of claim 6 wherein each of the multiple pixels further has an attached lens to direct light emitted from the pixel.”)).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kondo in view of Newell, in further view of Kozuma, and in further view of Seto et al. in US 2023/0047907 A1 (hereinafter Seto).
Regarding claim 19, Kondo as modified by Newell and Kozuma teaches:
The display device of claim 16.
However, it is noted that Kondo as modified by Newell and Kozuma, as particularly cited, does not teach:
wherein at least a portion of the first bridge line is connected to the second bridge line at the second conductive layer.
Seto teaches:
wherein at least a portion of a first bridge line (e.g., upper left 510 in FIG. 8) is connected to a second bridge line (e.g., 510 below upper left 510 in FIG. 8) at a second conductive layer (e.g., 510 layer below upper left 510 layer in FIG. 8) (Seto: see FIGs. 1 and 7-8, “[0047] The first wiring structure 512 can include a plurality of stacked conductive paths (wiring patterns…) 510, and an interlayer insulating film 511 arranged to insulate the plurality of conductive paths 510….”, and “[0054] FIG. 7 exemplifies the circuit arrangement of a pixel 102 of a light emitting device 101…. FIG. 8 exemplifies the sectional structure of the pixel 102 of the light emitting device 101…. [A] light emitting element 201 can be arranged on a second surface S2 of a first substrate 11…. [A] driving transistor 202 can be arranged in a second substrate 12….”, see also FIGs. 15-16).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to include: the features taught by Seto, such that Kondo as modified teaches: wherein at least a portion of the first bridge line is connected to the second bridge line at the second conductive layer (first and second bridge lines and second conductive layer of Kondo as modified combined with the first and second bridge lines and second conductive layer of Seto), for connecting a sub-pixel(s) to a pixel circuit(s) where the sub-pixel(s) overlap the pixel circuit(s).
Conclusion
Applicants’ amendments necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to K. Kiyabu whose telephone number is (571) 270-7836. The examiner can normally be reached Monday to Thursday 9:00 A.M. - 5:00 P.M. EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached at (571) 272-3017. The fax number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/K. K./
Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/Supervisory Patent Examiner, Art Unit 2626 2/23/26B