DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/23/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8, 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. U.S. Patent Publication No. 2021/0158751 (hereinafter Cha) in view of Yagi et al. U.S. Patent Publication No. 2022/0181366 (hereinafter Yagi) and further in view of Park et al. U.S. Patent Publication No. 2022/0344416 (hereinafter Park) and further view of Cha et al. U.S. Patent Publication No. 2022/0336561 (hereinafter Cha2).
Consider claim 1, Cha teaches a display device comprising: a display panel including a display region and a non-display region (Figure 5, DP-DA and DP-NDA), a plurality of pixels and a plurality of sensors being in the display region (Figure 5, PX and FX), wherein each of the plurality of pixels comprises: a light emitting element (Figure 8, LD); and a pixel drive circuit connected to the light emitting element (Figure 8, PXij and LD) and receiving a first drive voltage, a second drive voltage, and an initialization voltage (Figure 8, ELVDD, ELVSS and VINIT), wherein the plurality of sensors comprises first sensors in a first region of the display region and second sensors in a second region of the display region (Figure 5, plurality of FX), wherein each of the first sensors comprises: a first light receiving element (Figure 8, OPD); and a first sensor drive circuit electrically connected to the first light receiving element (Figure 8, OPD and ODC), wherein each of the second sensors comprises: a second light receiving element (Figure 8, OPD and ODC; Figure 5, plurality of FX); wherein each of the first and second sensor drive circuits comprises (Figure 5, plurality of FX): a reset transistor connected between a reset voltage line and a sensing node (Figure 8, FT1, FN and respective connections); an amplifying transistor connected to a sensor drive voltage line (Figure 8, FT2, ELVDD and respective connections); and an output transistor connected between the amplifying transistor and a readout line (Figure 8, FT3, FSj and respective connections), wherein the reset transistor and the amplifying transistor are transistors of different types from each other ([0134], a reset transistor FT1, an amplifying transistor FT2, and an output transistor FT3 may be P-type transistors such as a PMOS transistor, but are not limited thereto. At least one of the reset transistor FT1, the amplifying transistor FT2, or the output transistor FT3 may be an N-type transistor), wherein the sensor drive voltage line receive one of the first drive voltage or the initialization voltage as a sensor drive voltage (Figure 8, ODC and ELVDD).
Cha does not appear to specifically disclose a second sensor drive circuit electrically isolated from the second light receiving element.
However, in a related field of endeavor, Yagi teaches a sensor chip comprising pixels 21-22 in [0025] and figure 1, and further teaches a second sensor drive circuit electrically isolated from the second light receiving element (Figure 2, circuit 32-33 and light receiving element 31 for pixel 22).
Therefore, it would obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide pixel 22 as taught by Yagi with the benefit that pixel 22 is a dummy pixel. In addition, it is possible to prevent the occurrence of a phenomenon in which breakdowns continuously occur as suggested in [0045] and [0043].
Cha does not appear to specifically disclose wherein a gate electrode of the reset transistor and a gate electrode of the amplifying transistor are disposed on different insulating layers.
However, in a related field of endeavor, Park teaches a imaging sensor and display device (abstract and figure 1), and further teaches wherein a gate electrode of the reset transistor and a gate electrode of the amplifying transistor are disposed on different insulating layers (Figure 2b, M3 and M1. Figure 3, Gea and GE1 and 311-312).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide gates on different layers with the benefit that the first transistor M1 includes a gate connected to a cathode of the organic photodiode (OPD) and the third transistor M3 includes a gate connected to the reset signal line (RLb) as suggested in [0092] and [0094].
Cha does not appear to specifically disclose wherein the reset voltage line receives a reset voltage maintained at a voltage level lower than the second drive voltage.
However, in a related field of endeavor, Cha2 teaches a pixel driving circuit PDC and sensor driving circuit SDC in figure 5 and further teaches wherein the reset voltage line receives a reset voltage maintained at a voltage level lower than the second drive voltage [0111].
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular VRST voltage as taught by Cha2 so that reset transistor ST1 may reset an electric potential of the first sensing node SN1 to the reset voltage VRST in response to the compensating scan signal SCj. In addition, a particular voltage can be proved in order to meet design choice since Cha2 states that the reset voltage VRST may have the same voltage level as the voltage level corresponding to the activation period (i.e., the low level period) of the first and second writing scan signals SWj and SWj+1. The reset voltage VRST may be a DC voltage whose voltage level is lower than that of the second driving voltage ELVSS in [0111].
Consider claim 2, Cha, Yagi, Park and Cha2 teach all the limitations of claim 1. In addition, Cha teaches wherein the first light receiving element is electrically connected to the sensing node of the first sensor drive circuit (Figure 8, FN and OPD). In addition, Yagi teaches and wherein the second light receiving element is electrically isolated from the second sensor drive circuit at the sensing node of the second sensor drive circuit (Figure 2, 31 and 32-33 for pixel 22, see motivation to combine in claim 1).
Consider claim 3, Cha, Yagi, Park and Cha2 teach all the limitations of claim 2. In addition, Cha teaches wherein the reset transistor comprises a first electrode connected to the reset voltage line, a second electrode connected with the sensing node, and the gate electrode configured to receive a reset control signal (Figure 8, FT1 and respective connections), wherein the amplifying transistor comprises a first electrode connected to the sensor drive voltage line, a second electrode connected with the output transistor, and the gate electrode connected with the sensing node (Figure 8, FT2 and respective connections), and wherein the output transistor comprises a first electrode connected with the second electrode of the amplifying transistor, a second electrode connected with the readout line, and a gate electrode configured to receive an output control signal (Figure 8, FT3 and respective connections).
Consider claim 4, Cha, Yagi, Park and Cha2 teach all the limitations of claim 3. In addition, Cha teaches wherein a first effective connecting electrode is at the sensing node of the first sensor drive circuit to electrically connect the second electrode of the reset transistor and the gate electrode of the amplifying transistor (Figure 8, see connection at FN and FT1, FT2). In addition, Yagi teaches wherein a first ineffective connecting electrode is at the sensing node of the second sensor drive circuit and is not connected to at least one of the second electrode of the reset transistor or the gate electrode of the amplifying transistor (Figure 8, one electrode of 31 is not connected to at least one electrode of 32-33 for pixel 22, see motivation to combine in claim 1).
Consider claim 5, Cha, Yagi, Park and Cha2 teach all the limitations of claim 4. In addition, Cha teaches wherein the display panel further comprises: a first intermediate connecting electrode connected to the gate electrode of the amplifying transistor of the first sensor drive circuit (Figure 13, CNE3 and SCL2. [0175], the connection signal line SCL2 may be connected to the drain FD1 of the reset transistor FT1 (see also gate of FT2 and drain of FT1 in figure 8)); a second intermediate connecting electrode connected to the gate electrode of the amplifying transistor of the second sensor drive circuit (Figure 13, CNE3 and SCL2. [0175], the connection signal line SCL2 may be connected to the drain FD1 of the reset transistor FT1 (see also gate of FT2 and drain of FT1 in figure 8). Figure 5, plurality of FX); and a first via insulating layer (Figure 13, insulation 30), the first effective connecting electrode and the first ineffective connecting electrode being on the first via insulating layer (Figure 13, SCL2. Figure 5, plurality of FX), the first via insulating layer being on the first and second intermediate connecting electrodes (Figure 13, insulation 30 and CNE3).
Consider claim 6, Cha, Yagi, Park and Cha2 teach all the limitations of claim 5. In addition, Cha teaches wherein a first effective contact hole exposing the first intermediate connecting electrode is in the first via insulating layer (Figure 13, CNE3, SCL2, 30), and the first effective connecting electrode is connected to the first intermediate connecting electrode through the first effective contact hole (Figure 13, CNE3, SCL2, 30).
Cha does not appear to specifically disclose wherein the second intermediate connecting electrode is completely covered by the first via insulating layer without being exposed through a contact hole.
However, Yagi teaches wherein the second intermediate connecting electrode is completely covered by the first via insulating layer without being exposed through a contact hole (Figure 4, 74 and insulation between 74 and 53 (see figure 4 in comparison to figure 3) for pixel 22).
Therefore, it would obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide pixel 22 as taught by Yagi with the benefit that pixel 22 is a dummy pixel. In addition, it is possible to prevent the occurrence of a phenomenon in which breakdowns continuously occur as suggested in [0045] and [0043].
Consider claim 7, Cha, Yagi, Park and Cha2 teach all the limitations of claim 4. In addition, Cha teaches wherein a second effective connecting electrode connected to the first effective connecting electrode is further located at the sensing node of the first sensor drive circuit (Figure 13, CNE4 and CNE3), and wherein a second ineffective connecting electrode connected to the first ineffective connecting electrode is further located at the sensing node of the second sensor drive circuit (Figure 13, CNE4 and CNE3. Figure 5, plurality of FX).
Consider claim 8, Cha, Yagi, Park and Cha2 teach all the limitations of claim 7. In addition, Cha teaches wherein the first light receiving element comprises an effective anode electrode connected with the second effective connecting electrode of the first sensor drive circuit (Figure 13, CNE4 and E1. Figure 8, OPD), and wherein the second light receiving element comprises an ineffective anode electrode connected with the second ineffective connecting electrode of the second sensor drive circuit (Figure 13, CNE4 and E1. Figure 8, OPD. Figure 5, plurality of FX).
Consider claim 17, Cha, Yagi, Park and Cha2 teach all the limitations of claim 2. In addition, Cha teaches wherein the reset voltage line is commonly connected to the first and second sensor drive circuits (Figures 7-8, SC0-1 for first row of FXs), wherein the reset transistors of the first and second sensor drive circuits are concurrently turned on during a reset period (Figures 7-8, SC0-1 for first row of FXs), and wherein a reset voltage applied to the reset voltage line is applied to the sensing node through the turned-on reset transistors during the reset period (Figures 7-8, SC0-1 for first row of FXs).
Consider claim 18, Cha, Yagi, Park and Cha2 teach all the limitations of claim 1. In addition, Cha teaches wherein the first region is a sensing region configured to sense biometric information (Figure 5 and [0087], FX may be fingerprint sensing pixels).
Cha does not appear to specifically disclose wherein the second region is a non-sensing region configured so as not to sense the biometric information, and wherein the second region comprises: a first non-sensing region on a first side of the first region; and a second non-sensing region on a second side of the first region, the second side facing away from the first side of the first region.
However, Yagi teaches wherein the second region is a non-sensing region configured so as not to sense the biometric information (Figure 2, dummy pixels 22), and wherein the second region comprises: a first non-sensing region on a first side of the first region; and a second non-sensing region on a second side of the first region, the second side facing away from the first side of the first region (Figure 2, dummy pixels 22 and first region RA).
Therefore, it would obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide pixel 22 as taught by Yagi with the benefit that pixels 22 are dummy pixels. In addition, it is possible to prevent the occurrence of a phenomenon in which breakdowns continuously occur as suggested in [0045] and [0043].
Consider claim 19, Cha, Yagi, Park and Cha2 teach all the limitations of claim 1. In addition, Cha teaches wherein the display panel further comprises: readout lines connected to the sensors (Figure 8, FSj) and wherein the display device further comprises: a readout chip electrically connected to effective readout lines from among the readout lines (Figure 5, DP-PD and ISC), the effective readout lines being in the first region and connected to the first sensors (Figure 5, DP-PD and ISC).
Consider claim 20, Cha, Yagi, Park and Cha2 teach all the limitations of claim 19.
Cha does not appear to specifically disclose wherein the readout chip is not electrically connected with ineffective readout lines from among the readout lines, the ineffective readout lines being in the second region and connected to the second sensors.
However, Yagi teaches wherein the readout chip is not electrically connected with ineffective readout lines from among the readout lines (Figure 2, output of 33 for pixel 22. [0049-0050], arithmetic processing section; since the received light signals are not output from the SPAD pixels 22, the SPAD pixels 22 do not contribute to the generation of the above distance image), the ineffective readout lines being in the second region and connected to the second sensors (Figure 2, output of 33 for pixel 22).
Therefore, it would obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide pixel 22 as taught by Yagi with the benefit that pixels 22 are dummy pixels. In addition, it is possible to prevent the occurrence of a phenomenon in which breakdowns continuously occur as suggested in [0045] and [0043]. In addition, since the received light signals are not output from the pixels 22, the pixels 22 do not contribute to the generation of the above distance image as suggested in [0050].
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (see new reference Cha2).
Conclusion
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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