DETAILED ACTION
Claims 1-18 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in France on 10/19/23. It is noted, however, that applicant has not filed a certified copy of the FR2311320 application as required by 37 CFR 1.55.
The examiner would like to point out that the Interim Copy of the Foreign Priority Document filed on 01/27/2025 is not sufficient to comply with the priority claim under 35 U.S.C. 119(a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/16/24 and 11/5/24 has been considered by the examiner.
Drawings
The drawings were received on 10/16/24. These drawings are acceptable.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
means for measuring the resistance – what means that is used is not clearly stated in the specification – this also applies to the steps for measuring the resistance
means for carrying out – seen in Figure 4 and 5
means for determining – Paragraph [0164] The signals used to generate error information in order to determine the corrected word to be delivered are generated, on the one hand, by an ECC decoder carrying out decoding without inversion of weak-bits (signals denoted “outdec1”, “n-errordec1” and “uncorrectable errordec1”), and are generated, on the other hand, by an ECC decoder carrying out decoding with inversion of weak-bits (signals denoted “outdec2”, “n-errordec2” and “uncorrectable errordec2”).
means for selecting – Figure 6
means for identifying weak-bits (claim 6) - what means that is used is not clearly stated in the specification - this also applies to the steps for identifying the weak bits.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitations “means for measuring the resistance” (claims 1, 4, 5, and 15) and “means for identifying weak-bits” (1, 6 and 15) invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. It is unclear to the examiner what structure performs these functions. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 2-14 and 16-18 depend directly or indirectly on the independent claims 1 and 15. As such these claims are also rejected for the same reasoning, and may not be further considered with respect to the prior arts. Clarification is required.
Examiner’s note: The examiner would like to point out that as paragraph [0026] states: “The article by V. Gherman, L. Ciampolini, S. Evain and S. Ricavy entitled, “Error Correction Improvement based on Weak-bit-Flipping for Resistive Memories”, Microelectronics Reliability, volume 136, 2022, describes a method and devices for identifying weak-bits and increasing the correction capacity of an ECC based on identifying weak-bits. However essential subject matter cannot be incorporated by reference (no incorporation by reference has been claimed in this application).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160179616 to Ha et al. in view of Valentin et al: "Error correction improvement based on weak-bit flipping for resistive memories".
As per claim 1 Ha et al. substantially teach the claimed device for reading a code word stored in a resistive memory where each memory cell comprises resistive devices for storing a bit of a code word (Paragraph [0017] and Abstract flash memory encoded with BCH), the reading device comprising:
means for measuring the resistance of each resistive device storing a bit of a code word to be read, and for identifying weak-bits (paragraph [0023] bits with low reliability, determination of weak bits by three readings of the flash memory, identifying high-reliability bits and low-reliability bits, among which p low-reliability bits are chosen, for example, randomly, p < nu, Paragraphs [0082-0084]);
means for carrying out, with an error-correcting code decoder having a maximum correction capacity of n erroneous bits, a first and a second process of decoding the code word, with the first and second decoding processes being carried out without and with inversion (flipping) of the weak-bits (Fig. 5: step S501 "Perform Hard Decision Decoding" - corresponding to the first decoding, and step S513 "Perform Soft Decision Decoding" - corresponding to the second decoding. It should be noted that in step S513 of soft decoding based on the Chase algorithm, 2P test error patterns are formed, and 2P decodings are performed after inversion of the least significant bits corresponding to each test error pattern. Therefore, step Fig 5 S513 itself comprises a first decoding and 2P-1 second decodings respectively with and without inversion of the least significant bits), respectively;
means for determining, in each version of the decoded code word, information concerning the number of errors, with respect to errors that are detectable but uncorrectable according to the correction capacity of said error-correcting code (Paragraph [0051]) and with respect to errors that are correctable according to the correction capacity of said error-correcting code and that affect a maximum number of erroneous bits (Fig 5 step S505 "Hard Decoding Succeeded?". This decision constitutes information on the number of errors for the "first decoding" since the decision "N" -decoding not successful - implies that the number of errors is greater than the decoding capacity of a BCH code. It should be noted that the "error count information" also included in the application in claim 3, the case where this information simply indicates that the decoding is not possible. Chase decoding in step S513 includes 2P hard decodings and a selection step among the decoding results - inherent to the Chase algorithm.); and
means for selecting the version of the decoded code word that contains the fewest erroneous bits as a function of the information concerning the number of errors (The examiner would like to point out that when attempting to prevent/correct errors it would be obvious to select the version of the decoded code word that contains the fewest erroneous bits from a reliability standpoint of the memory in question).
Not taught by Ha et al. is a resistive memory device and measuring the resistance of each resistive device. However in an analogous art Valentin et al. teach error correction in resistive memories (Section 1 Introduction, paragraph 2) and measuring the resistance values (Section 4 Weak- bit identification in 2T2R memories based on additional sensing in 1T1R mode paragraph 1-3).
Therefore the use of resistive memories is a well-known alternative to flash memories. A person having ordinary skill in the art at the time of filing of the present application, would have known that Valentin et al. and Ha et al. both reading the memory and determining weak bits in a manner adapted to such memories (resistive or flash). A person skilled in the art would know that Ha et al. teaches determining the weak bits based on a plurality of readings with different voltage thresholds. Valentin et al. teach determining the weak bits based on a plurality of readings with different resistance thresholds. As such it would be obvious to use resistive memories with the error correction of Ha et al.
As per claim 15, this independent claim is the method claim implemented by the device of claim 1 and is therefore rejected for the same reasoning as claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior arts of record:
US 11799496 to Kwak teaches transmitting flip bits to a flip decision component over a first output line coupling the flip bit error correction component and the flip decision component; performing a bit error correction procedure on one or more data bits; and transmitting, by the data bit error correction component, the data bits to the flip decision component over a second output line based at on performing the bit error correction procedure.
US 11775383 to Fackenthal teaches performing error correction of data bits in a codeword concurrently with the generation of a flip bit that indicates whether data bits in a corresponding codeword are to be flipped; for refraining from performing error correction of inversion bit(s) in the codeword; and for generating a high-reliability flip bit using multiple inversion bits.
US 11755411 to Roy et al. teaches an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant of each other; and a memory controller. The memory controller is configured to, for each of the words, set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a zero value is greater than the number of data bit cells having a one value, invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and revert the data bit cells to their value before the zeroes and ones were inverted.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA H BRITT whose telephone number is (571)272-3815. The examiner can normally be reached Monday - Thursday 8-5.
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CYNTHIA H. BRITT
Primary Examiner
Art Unit 2111
/CYNTHIA BRITT/Primary Examiner, Art Unit 2111