DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 07/14/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-15 and 17 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The current amended claim 1 includes claim limitations “the array substrate is provided with: a plurality of pixel electrodes disposed in the array substrate, a common electrode disposed overlapping the plurality of pixel electrodes, an insulating film disposed on an upper layer side of the common electrode, and an alignment film disposed on an upper layer side of the insulating film, each of a plurality of thin film transistors is connected to a corresponding one of the plurality of pixel electrodes, a line extends in a first direction and is connected to gate electrodes of the plurality of thin film transistors, a light blocking portion and a spacer are provided in at least one of the array substrate and the counter substrate, the light blocking portion including a first light blocking portion extending in the first direction, and the spacer being disposed overlapping the first light blocking portion, a connection electrode is connected to the common electrode through an opening provided in the insulating film, the alignment film is in contact with the connection electrode, the opening is disposed at a position that overlaps the first light blocking portion, each of the plurality of pixel electrodes and the connection electrode are disposed on a lower layer side of the alignment film and on the upper layer side of the insulating film, the plurality of pixel electrodes is disposed in the first direction and a second direction intersecting the first direction, the connection electrode is positioned between two pixel electrodes of the plurality of pixel electrodes that are adjacent to each other in the second direction, the spacer protrudes toward a liquid crystal layer side from the counter substrate, the array substrate is further provided with an organic material film disposed on the lower layer side of the alignment film and on upper layer sides of each of the plurality of pixel electrodes and the connection electrode, the organic material film is disposed overlapping the spacer, and the connection electrode is disposed such that the connection electrode does not overlap the organic material film” raised new matter issue, because only figs.17-19 includes the feature of “the connection electrode is disposed such that the connection electrode does not overlap the organic material film” and figs.17-19 discloses “the connection electrode (40) is positioned between two pixel electrodes of the plurality of pixel electrodes that are adjacent to each other in the first direction (X axis) (Y axis), not in the second direction”, and the other embodiments figs.20-30 having the portion (42, 542, 642) of the connection electrode overlaps the organic material film and the spacer (330, 530, 630).
Also, dependent claims 2-15 and 17 are rejected by virtue of their dependency.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 and 17 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 13, the claim limitations, “the array substrate is provided with: a plurality of pixel electrodes disposed in the array substrate, a common electrode disposed overlapping the plurality of pixel electrodes, an insulating film disposed on an upper layer side of the common electrode, and an alignment film disposed on an upper layer side of the insulating film, each of a plurality of thin film transistors is connected to a corresponding one of the plurality of pixel electrodes, a line extends in a first direction and is connected to gate electrodes of the plurality of thin film transistors, a light blocking portion and a spacer are provided in at least one of the array substrate and the counter substrate, the light blocking portion including a first light blocking portion extending in the first direction, and the spacer being disposed overlapping the first light blocking portion, a connection electrode is connected to the common electrode through an opening provided in the insulating film, the alignment film is in contact with the connection electrode, the opening is disposed at a position that overlaps the first light blocking portion, each of the plurality of pixel electrodes and the connection electrode are disposed on a lower layer side of the alignment film and on the upper layer side of the insulating film, the plurality of pixel electrodes is disposed in the first direction and a second direction intersecting the first direction, the connection electrode is positioned between two pixel electrodes of the plurality of pixel electrodes that are adjacent to each other in the second direction, the spacer protrudes toward a liquid crystal layer side from the counter substrate, the array substrate is further provided with an organic material film disposed on the lower layer side of the alignment film and on upper layer sides of each of the plurality of pixel electrodes and the connection electrode, the organic material film is disposed overlapping the spacer, and the connection electrode is disposed such that the connection electrode does not overlap the organic material film” are considered to be indefinite.
The original disclosure only figs.17-19 includes the feature of “the connection electrode is disposed such that the connection electrode does not overlap the organic material film” and figs.17-19 discloses “the connection electrode (40) is positioned between two pixel electrodes of the plurality of pixel electrodes that are adjacent to each other in the first direction (X axis) (Y axis), not in the second direction”. Also, the other embodiments figs.20-30 having the portion (42, 542, 642) of the connection electrode overlaps the organic material film and the spacer (330, 530, 630). Therefore, it is indefinite.
For the purpose of examination, the examiner will interpret the above limitation as - - “the array substrate is provided with: a plurality of pixel electrodes disposed in the array substrate, a common electrode disposed overlapping the plurality of pixel electrodes, an insulating film disposed on an upper layer side of the common electrode, and an alignment film disposed on an upper layer side of the insulating film, each of a plurality of thin film transistors is connected to a corresponding one of the plurality of pixel electrodes, a line extends in a first direction and is connected to gate electrodes of the plurality of thin film transistors, a light blocking portion and a spacer are provided in at least one of the array substrate and the counter substrate, the light blocking portion including a first light blocking portion extending in the first direction, and the spacer being disposed overlapping the first light blocking portion, a connection electrode is connected to the common electrode through an opening provided in the insulating film, the alignment film is in contact with the connection electrode, the opening is disposed at a position that overlaps the first light blocking portion, each of the plurality of pixel electrodes and the connection electrode are disposed on a lower layer side of the alignment film and on the upper layer side of the insulating film, the plurality of pixel electrodes is disposed in the first direction and a second direction intersecting the first direction, the connection electrode is positioned between two pixel electrodes of the plurality of pixel electrodes that are adjacent to each other in the first direction, the spacer protrudes toward a liquid crystal layer side from the counter substrate, the array substrate is further provided with an organic material film disposed on the lower layer side of the alignment film and on upper layer sides of each of the plurality of pixel electrodes and the connection electrode, the organic material film is disposed overlapping the spacer, and the connection electrode is disposed such that the connection electrode does not overlap the organic material film” - -.
Also, dependent claims 2-15 and 17 are rejected by virtue of their dependency.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 19 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 2 and 5 of U.S. Patent No. 12,153,299 in view of Woo US 20160313614.
Regarding claim 19, claims 1, 2 and 5 of U.S. Patent No. 12,153,299 teaches all the claim limitations of claim 19, except, the connection electrode includes a portion that does not overlap the spacer.
Woo US 20160313614 discloses a liquid crystal panel, in at least figs.1, 2 and 6A-9, the connection electrode (CNT1 and CNT2 or CNT, para.58, 64 and 71 disclose CNT may overlap both the date line DL and the spacer and the size of the conductive connectors can be changed, so CNT1 and CNT2 can be connected to each other like CNT, or CNT can increase size to overlap both CNT1 and CNT2) includes a portion that does not overlap the spacer) includes a portion (CNT1) that does not overlap the spacer (CS) for the purpose of preventing an increase in a height difference in a connection portion between the alignment layer PI and the common electrode COM (para.63).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the connection electrode includes a portion that does not overlap the spacer as taught by Woo in the liquid crystal panel of claims 1, 2 and 5 of U.S. Patent No. 12,153,299 for the purpose of preventing an increase in a height difference in a connection portion between the alignment layer PI and the common electrode COM (para.63).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Woo US 20160313614.
Regarding claim 19, Woo discloses a liquid crystal panel, in at least figs.1, 2, 6A-10, 12 and 13, comprising:
an array substrate (lower substate, see figs.8, 9 and 13);
a counter substrate (upper substrate, see figs.8, 9 and 13) disposed facing the array substrate; and
a liquid crystal layer (layer with nLC) sandwiched between the array substrate and the counter substrate,
wherein the array substrate is provided with a plurality of pixel electrodes (PXL) disposed in the array substrate (figs.6A-9 and 13),
a common electrode (COM) disposed overlapping the plurality of pixel electrodes,
an insulating film (PAS1) disposed on an upper layer side of the common electrode, and
an alignment film (PI) disposed on an upper layer side of the insulating film,
each of a plurality of thin film transistors (TFT) is connected to a corresponding one of the plurality of pixel electrodes (see figs.1, 7 and 9),
a line (GL) extends in a first direction (horizontal direction) and is connected to gate electrodes of the plurality of thin film transistors (see figs.1, 6A-9 and 13),
a light blocking portion (BM) and a spacer (CS) are provided in at least one of the array substrate and the counter substrate (see figs.8, 9 and 13), the light blocking portion including a first light blocking portion (portion extending in the first direction) extending in the first direction, and the spacer being disposed overlapping the first light blocking portion (see figs.8, 9 and 13),
a connection electrode (CNT1 and CNT2 or CNT, para.58, 64 and 71 disclose CNT may overlap both the date line DL and the spacer and the size of the conductive connectors can be changed, so CNT1 and CNT2 can be connected to each other like CNT, or CNT can increase size to overlap both CNT1 and CNT2) is connected to the common electrode through an opening provided in the insulating film (see fig.9),
the alignment film is in contact with the connection electrode (see fig.9),
the opening is disposed at a position that overlaps the first light blocking portion (see figs.6E, 7 and 9),
each of the plurality of pixel electrodes and the connection electrode are disposed on a lower layer side of the alignment film and on the upper layer side of the insulating film (see fig.9),
the plurality of pixel electrodes is disposed in the first direction and a second direction intersecting the first direction (see at least figs.1 and 7), and
the connection electrode (CNT2 portion of the connection electrode) is positioned between two pixel electrodes of the plurality of pixel electrodes that are adjacent to each other in the second direction (vertical direction) (see figs.6E, 7 and 9), includes a portion (CNT1) that does not overlap the spacer (see figs.6E and 9).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-9, 11, 13, 14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo US 20160313614 in view of Liu US 2016/0202570.
Regarding claim 1, Woo discloses a liquid crystal panel, in at least figs.1, 2, 6A-10, 12 and 13, comprising:
an array substrate (lower substate, see figs.8, 9 and 13);
a counter substrate (upper substrate, see figs.8, 9 and 13) disposed facing the array substrate; and
a liquid crystal layer (layer with nLC) sandwiched between the array substrate and the counter substrate,
wherein the array substrate is provided with a plurality of pixel electrodes (PXL) disposed in the array substrate (figs.6A-9 and 13),
a common electrode (COM) disposed overlapping the plurality of pixel electrodes,
an insulating film (PAS1) disposed on an upper layer side of the common electrode, and
an alignment film (PI) disposed on an upper layer side of the insulating film,
each of a plurality of thin film transistors (TFT) is connected to a corresponding one of the plurality of pixel electrodes (see figs.1 and 7-9),
a line (GL) extends in a first direction (horizontal direction) and is connected to gate electrodes of the plurality of thin film transistors (see figs.1, 6A-9 and 13),
a light blocking portion (BM) and a spacer (CS) are provided in at least one of the array substrate and the counter substrate (see figs.8, 9 and 13), the light blocking portion including a first light blocking portion (portion extending in the first direction) extending in the first direction, and the spacer being disposed overlapping the first light blocking portion (see figs.8, 9 and 13),
a connection electrode (CNT1 or CNT) is connected to the common electrode through an opening provided in the insulating film (see figs.8 and 9),
the alignment film is in contact with the connection electrode (see figs.8 and 9),
the opening is disposed at a position that overlaps the first light blocking portion (see figs.6A-9),
each of the plurality of pixel electrodes and the connection electrode are disposed on a lower layer side of the alignment film and on the upper layer side of the insulating film (see figs.8 and 9),
the plurality of pixel electrodes is disposed in the first direction and a second direction intersecting the first direction (see at least figs.1 and 7), and
the connection electrode is positioned between two pixel electrodes of the plurality of pixel electrodes that are adjacent to each other in the first direction (see figs.6A-6E),
the spacer protrudes toward a liquid crystal layer side from the counter substrate (see figs.8 and 9), and
the connection electrode does not overlap the spacer (see figs.8 and 9).
Woo does not explicitly disclose the array substrate is further provided with an organic material film disposed on the lower layer side of the alignment film and on upper layer sides of each of the plurality of pixel electrodes and the connection electrode, the organic material film is disposed overlapping the spacer, and the connection electrode is disposed such that the connection electrode does not overlap the organic material film.
Liu discloses a liquid crystal panel, in at least figs.3-6, the array substrate (100) is further provided with an organic material film (112, para.11, acrylic material) disposed on the lower layer side of the alignment film (114) and on upper layer sides of each of the plurality of pixel electrodes (110), the organic material film is disposed overlapping the spacer (302) for the purpose of forming a planarization layer on the pixel electrode layer (para.10) and improving optical properties of the display such as contrast ratio (para.14).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the array substrate is further provided with an organic material film disposed on the lower layer side of the alignment film and on upper layer sides of each of the plurality of pixel electrodes, the organic material film is disposed overlapping the spacer as taught by Liu in the liquid crystal panel of Woo in order to have the array substrate is further provided with an organic material film disposed on the lower layer side of the alignment film and on upper layer sides of each of the plurality of pixel electrodes and the connection electrode, the organic material film is disposed overlapping the spacer, and the connection electrode is disposed such that the connection electrode does not overlap the organic material film because Woo has the connection electrode on the lower layer side of the alignment film and has the same upper layer side as the pixel electrode and the connection electrode does not overlap the spacer for the purpose of forming a planarization layer on the pixel electrode layer and improving optical properties of the display such as contrast ratio.
Regarding claim 2, Woo discloses the opening is disposed at a position that does not overlap the spacer (see figs.8 and 9).
Regarding claim 3, Woo discloses the connection electrode includes a transparent electrode film (see para.76).
Regarding claim 5, Woo discloses each of the plurality of pixel electrodes includes a first portion of a transparent electrode film (para.76), and the connection electrode includes a second portion of the transparent electrode film which is separate from each of the plurality of pixel electrodes (para.76 and figs.8 and 9).
Regarding claim 6, Woo discloses a film thickness of the insulating film is larger than a film thickness of the connection electrode (see figs.8 and 9).
Regarding claim 7, Woo discloses at least a portion of the opening is disposed overlapping the line (see figs.6A-9).
Regarding claim 8, Woo discloses the first light blocking portion is disposed overlapping the line (see figs.7-9).
Regarding claim 9, Woo discloses the light blocking portion further includes a second light blocking portion extending in the second direction (see figs.7-9), and the spacer is further disposed to overlap to an intersection of the first light blocking portion and the second light blocking portion (see figs.7-9).
Regarding claim 11, Woo discloses the light blocking portion further includes a second light blocking portion (a portion overlap date line DL) extending in the second direction (see figs.7-9), and the second light blocking portion is narrower than the first light blocking portion (see figs.7-9).
Regarding claim 13, Woo discloses the connection electrode has a rectangular shape when viewed in a plan view (see figs.6A-7).
Regarding claim 14, Woo discloses the array substrate is further provided with a flattening film (PAC) disposed on a lower layer side of the common electrode, and the flattening film has a film thickness larger than a film thickness of the insulating film and is disposed overlapping the spacer (see figs.8 and 9).
Regarding claim 17, Liu discloses the organic material film (112) has a film thickness larger than the film thickness of the insulating film (134)(see fig.3) for the purpose of forming a planarization layer on the pixel electrode layer (para.10) and improving optical properties of the display such as contrast ratio (para.14). The reason for combining is the same as claim 1.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo US 20160313614 in view of Liu US 2016/0202570 as applied to claim 3 above,
Regarding claim 4, Woo discloses the transparent electrode film has a film thickness (see figs.8 and 9).
Woo in view of Liu does not explicitly disclose of the film thickness approximately 0.05 μm to 0.1 μm. However, one of ordinary skill in the art would have been led to the film thickness approximately 0.05 μm to 0.1 μm through routine experimentation and optimization, in re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). The Applicant has not disclosed that the range is for a particular unobvious purpose, produce an unexpected/significant result, or are otherwise critical, and it appears prima facie that the process would possess utility using another range. Indeed, it has been held that mere range limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the film thickness approximately 0.05 μm to 0.1 μm in the liquid crystal panel of Woo in view of Liu for the purpose of reducing material cost and having high transparency.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo US 20160313614 in view of Liu US 2016/0202570 as applied to claim 9 above, and further in view of Kamitani US 2019/0227391.
Regarding claim 10, Woo discloses the first light blocking portion is one of a plurality of first light blocking portions (see figs.1 and 6A-9), the second light blocking portion is one of a plurality of second light blocking portions (see figs.1 and 6A-9), the spacer is one of a plurality of the spacers (see figs.1 and 6A-9).
Woo in view of Liu does not explicitly disclose a number of the plurality of spacers is smaller than a number of intersections of the plurality of first light blocking portions and the plurality of second light blocking portions.
Kamitani discloses a liquid crystal panel, in at least figs.2-4, a number of the plurality of spacers (25 with 26) is smaller than a number of intersections (see figs.2 and 3) of the plurality of first light blocking portions (51) and the plurality of second light blocking portions (52)(see figs.2 and 3 and para.7, 38 and 59) for the purpose of defining the cell gap of the liquid crystal panel (para.6) and improving pressure force resistance property without decreasing the aperture ratio (para.80).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a number of the plurality of spacers is smaller than a number of intersections of the plurality of first light blocking portions and the plurality of second light blocking portions as taught by Kamitani in the liquid crystal panel of Woo in view of Liu for the purpose of defining the cell gap of the liquid crystal panel and improving pressure force resistance property without decreasing the aperture ratio.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo US 20160313614 in view of Liu US 2016/0202570 as applied to claim 1 above, and further in view of Kamitani US 2019/0227391.
Regarding claim 12, Woo in view of Liu does not explicitly disclose the spacer includes a first spacer and a second spacer, the first spacer has a diameter that is smaller than a diameter of the second spacer.
Kamitani discloses a liquid crystal panel, in at least figs.2-4, the spacer includes a first spacer (25) and a second spacer (26), the first spacer has a diameter (D1) that is smaller than a diameter (D2) of the second spacer for the purpose of defining the cell gap of the liquid crystal panel (para.6) and improving pressure force resistance property without decreasing the aperture ratio (para.80).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the spacer includes a first spacer and a second spacer, the first spacer has a diameter that is smaller than a diameter of the second spacer as taught by Kamitani in the liquid crystal panel of Woo in view of Liu for the purpose of defining the cell gap of the liquid crystal panel and improving pressure force resistance property without decreasing the aperture ratio.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo US 20160313614 in view of Liu US 2016/0202570 as applied to claim 1 above, and further in view of Morinaga US 2021/0278921.
Regarding claim 15, Woo in view of Liu does not explicitly disclose the common electrode is one of a plurality of common electrodes disposed side by side at intervals in the first direction and the second direction.
Morinaga discloses a liquid crystal panel, in at least fig.1, the common electrode (25) is one of a plurality of common electrodes (30) disposed side by side at intervals in the first direction (X-direction) and the second direction (Y-direction)(see fig.1) for the purpose of having a liquid crystal panel having with touch panel function for detecting a position to be input by the user based on a displayed image (para.48).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the common electrode is one of a plurality of common electrodes disposed side by side at intervals in the first direction and the second direction as taught by Morinaga in the liquid crystal panel of Woo in view of Liu for the purpose of having a liquid crystal panel with touch panel function for detecting a position to be input by the user based on a displayed image.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo US 20160313614 in view of Liu US 2016/0202570 as applied to claim 1 above, and further in view of Yoshida US 20200159354.
Regarding claim 15, Woo in view of Liu does not explicitly disclose the common electrode is one of a plurality of common electrodes disposed side by side at intervals in the first direction and the second direction.
Yoshida discloses a liquid crystal panel, in at least figs.1-4, the common electrode (11h) is one of a plurality of common electrodes (14) disposed side by side at intervals in the first direction (X-direction) and the second direction (Y-direction) (see fig.1) for the purpose of having a liquid crystal panel with touch panel function for detecting a position to be input by the user based on a displayed image (para.36).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the common electrode is one of a plurality of common electrodes disposed side by side at intervals in the first direction and the second direction as taught by Yoshida in the liquid crystal panel of Woo in view of Liu for the purpose of having a liquid crystal panel with touch panel function for detecting a position to be input by the user based on a displayed image.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Woo US 20160313614 in view of Ding US 2016/0320650.
Regarding claim 19, Woo discloses a liquid crystal panel, in at least figs.1, 2, 6A-10, 12 and 13, comprising:
an array substrate (lower substate, see figs.8, 9 and 13);
a counter substrate (upper substrate, see figs.8, 9 and 13) disposed facing the array substrate; and
a liquid crystal layer (layer with nLC) sandwiched between the array substrate and the counter substrate,
wherein the array substrate is provided with a plurality of pixel electrodes (PXL) disposed in the array substrate (figs.6A-9 and 13),
a common electrode (COM) disposed overlapping the plurality of pixel electrodes,
an insulating film (PAS1) disposed on an upper layer side of the common electrode, and
an alignment film (PI) disposed on an upper layer side of the insulating film,
each of a plurality of thin film transistors (TFT) is connected to a corresponding one of the plurality of pixel electrodes (see figs.1, 7 and 9),
a line (GL) extends in a first direction (horizontal direction) and is connected to gate electrodes of the plurality of thin film transistors (see figs.1, 6A-9 and 13),
a light blocking portion (BM) and a spacer (CS) are provided in at least one of the array substrate and the counter substrate (see figs.8, 9 and 13), the light blocking portion including a first light blocking portion (portion extending in the first direction) extending in the first direction, and the spacer being disposed overlapping the first light blocking portion (see figs.8, 9 and 13),
a connection electrode (CNT2) is connected to the common electrode through an opening provided in the insulating film (see fig.9),
the alignment film is in contact with the connection electrode (see fig.9),
the opening is disposed at a position that overlaps the first light blocking portion (see figs.6E, 7 and 9),
each of the plurality of pixel electrodes and the connection electrode are disposed on a lower layer side of the alignment film and on the upper layer side of the insulating film (see fig.9),
the plurality of pixel electrodes is disposed in the first direction and a second direction intersecting the first direction (see at least figs.1 and 7), and
the connection electrode is positioned between two pixel electrodes of the plurality of pixel electrodes that are adjacent to each other in the second direction (vertical direction) (see figs.6E, 7 and 9).
Woo does not explicitly disclose the connection electrode includes a portion that does not overlap the spacer.
Ding discloses a liquid crystal panel, in at least figs.1-10 and 26, the connection electrode (M31 and M32) includes a portion (M31) overlapping the data line (D3) between two adjacent pixel electrodes (Px1 and Px2) and another portion (M32) overlapping the gate line (G2)(para.47 and figs.1, 6 and 26 and abstract) for the purpose of suppressing the electric field leakage of the data line and the gate line and reducing the light leakage of the display panel (para.125).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the connection electrode includes a portion overlapping the data line between two adjacent pixel electrodes and another portion overlapping the gate line as taught by Ding in the liquid crystal panel of Woo in order to have the connection electrode includes a portion that does not overlap the spacer for the purpose of suppressing the electric field leakage of the data line and the gate line and reducing the light leakage of the display panel.
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The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jeong US 20130057813 (figs.1-8) discloses connection electrode (Scom) and Hwang US 2013/0234143 (at least figs.2-5) discloses connection electrode (136) can be a secondary reference too.
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/JIA X PAN/Primary Examiner, Art Unit 2871
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