Prosecution Insights
Last updated: August 30, 2026
Application No. 18/918,956

METHOD FOR MANUFACTURING MULTILAYER PRINTED WIRING BOARD AND MULTILAYER PRINTED WIRING BOARD

Non-Final OA §102
Filed
Oct 17, 2024
Priority
Nov 13, 2019 — provisional 62/934,632 +2 more
Examiner
BURNS, TREMESHA WILLIS
Art Unit
Tech Center
Assignee
Panasonic Holdings Corporation
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
695 granted / 890 resolved
+18.1% vs TC avg
Strong +17% interview lift
Without
With
+17.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
50 currently pending
Career history
938
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
33.6%
-6.4% vs TC avg
§102
46.5%
+6.5% vs TC avg
§112
18.2%
-21.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 890 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishikawa (WO 2007/116685). Regarding claim 1, in Figure 5, Nishikawa discloses a method for manufacturing a multilayer printed wiring board, the method comprising: providing a first laminate (comprising bottom layers 2, 1, and 4) and a second laminate (comprising upper layers 2, 1, and 4), the first laminate including a first conductor layer (bottom layer 2), a first insulating layer (bottom layer 1) containing polyimide, and a second conductor layer (bottom layer 4) which are stacked one on top of another in this order, the second laminate including a second insulating layer (upper layer 1) containing polyimide and a third conductor layer (upper layer 2) which are stacked one on top of the other in this order; heating each of the first laminate and the second laminate under a condition including a heating temperature equal to or higher than 100°C and a heating duration equal to or longer than half an hour (claim 22); and stacking, after heating, the first laminate and the second laminate one on top of the other with a third insulating layer (3) interposed between the second conductor layer and the second insulating layer. Regarding claim 2, Nishikawa discloses placing, in an interval from an end of the heating to a beginning of the stacking, the first laminate and the second laminate in an atmosphere having a temperature equal to or higher than 18oC and equal to or lower than 28oC and a relative humidity equal to or less than 65% RH for at most one hour (Figure 2). Regarding claim 3, Nishikawa discloses wherein a weight variation measured by dry weight measurement method with a total volume of the first insulating layer, the second insulating layer, and the third insulating layer defined as a reference is equal to or less than 3000 μg/cm3 (Figure 2). Regarding claim 4, Nishikawa discloses wherein the first insulating layer and the second insulating layer each have a thickness equal to or greater than 25 μm and equal to or less than 500 μm (Figure 2). Regarding claim 5, Nishikawa discloses wherein a ratio of a total thickness of the first insulating layer and the second insulating layer to a total thickness of the first insulating layer, the second insulating layer, and the third insulating layer is equal to or greater than 67% (Figure 2). Regarding claim 6, Nishikawa discloses wherein an insulating layer thickness X, which is a sum of respective thicknesses of the first insulating layer, the second insulating layer, and the third insulating layer, is equal to or greater than 75 μm and equal to or less than 125 μm, and a transmission loss Y of the multilayer printed wiring board meets the following inequality (1): 0 > Y ≥ 0.6175X – 126.26 (1) and is equal to or greater than –80 (Figure 2). Regarding claim 7, Nishikawa discloses wherein an insulating layer thickness X, which is a sum of respective thicknesses of the first insulating layer, the second insulating layer, and the third insulating layer, is equal to or greater than 125 μm and equal to or less than 200 μm, and a transmission loss Y of the multilayer printed wiring board meets the following inequality (2): 0 > Y ≥ 0.1532X – 68.221 (2) and is equal to or greater than –49 (Figure 2). Regarding claim 8, Nishikawa discloses wherein an insulating layer thickness X, which is a sum of respective thicknesses of the first insulating layer, the second insulating layer, and the third insulating layer, is equal to or greater than 200 μm and equal to or less than 325 μm, and a transmission loss Y of the multilayer printed wiring board meets the following inequality (3): 0 > Y ≥ 0.1028X – 58.135 (3) and is equal to or greater than –38 (Figure 2). Regarding claim 9, Nishikawa discloses wherein an insulating layer thickness X, which is a sum of respective thicknesses of the first insulating layer, the second insulating layer, and the third insulating layer, is equal to or greater than 325 μm and equal to or less than 1025 μm, and a transmission loss Y of the multilayer printed wiring board meets the following inequality (4): 0 > Y ≥ 0.0113X – 28.397 (4) and is equal to or greater than –25 (Figure 2). Regarding claim 10, Nishikawa discloses wherein the third insulating layer has a dielectric constant equal to or less than 2.9, and the third insulating layer has a dielectric loss tangent equal to or less than 0.003 (Figure 2). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Oct 17, 2024
Application Filed
Aug 12, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.3%)
2y 6m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 890 resolved cases by this examiner. Grant probability derived from career allowance rate.

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