Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of Patent Application 18918959 on 10/17/2024.
Claim Rejections - 35 USC § 101
1. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claim(s) 1 is/are drawn to method (i.e., a process), claim(s) 11, 20 is/are drawn to a system (i.e., a machine/manufacture).
Claims 1, 3-20 are directed to deriving virtual address via offsets. Specifically, the claims recite determining an offset of the first virtual address from a first base address associated with the first set of contiguous virtual addresses; translating the first virtual address to a corresponding multicast virtual address based on the offset, wherein the multicast virtual address is included in a second set of contiguous virtual addresses for multicast operations, and wherein the multicast virtual address is located at the offset from a second base address associated with the second set of contiguous virtual addresses wherein the at least one processing element is associated with the first set of continuous virtual addresses and the second set of contiguous virtual addresses, and wherein the first set of contiguous virtual addresses and the second set of contiguous virtual addresses are respectively symmetric; and causing the collective operation to be performed based at least on the multicast virtual address., which is grouped within the Methods Of Organizing Human Activity and is similar to the concept of (fundamental economic principles or practices including hedging insurance, mitigating risk) OR (commercial or legal interactions including agreements in the form of contracts, legal obligations, advertising, marketing or sales activities or behaviors business relations) OR (managing personal behavior or relationships or interactions between people including social activities teaching, and following rules or instructions) OR Mental Processes and is similar to the concept of (concepts performed in the human mind (including an observation, evaluation, judgement, opinion) grouping of abstract ideas in prong one of step 2A of the Alice/Mayo test (See 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50, 52, 54 (January 7, 2019)). Accordingly, the claims recite an abstract idea (See pages 7, 10, Alice Corporation Pty. Ltd. v. CLS Bank International, et al., US Supreme Court, No. 13-298, June 19, 2014; 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50, 53-54 (January 7, 2019)).
This judicial exception is not integrated into a practical application because, when analyzed under prong two of step 2A of the Alice/Mayo test (See 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50, 54-55 (January 7, 2019)), the additional element(s) of the claim(s) such as memory and a processor merely use(s) a computer as a tool to perform an abstract idea and/or generally link(s) the use of a judicial exception to a particular technological environment. Specifically, the memory and a processor perform(s) the steps or functions of receiving an instruction for performing a collective operation across at least one processing element, wherein the instruction specifies a first virtual address that is included in a first set of contiguous virtual addresses for unicast operations. The use of a processor/computer as a tool to implement the abstract idea and/or generally linking the use of the abstract idea to a particular technological environment does not integrate the abstract idea into a practical application because it requires no more than a computer performing functions that correspond to acts required to carry out the abstract idea. The additional elements do not involve improvements to the functioning of a computer, or to any other technology or technical field (MPEP 2106.05(a)), the claims do not apply or use the abstract idea to effect a particular treatment or prophylaxis for a disease or medical condition (Vanda Memo), the claims do not apply the abstract idea with, or by use of, a particular machine (MPEP 2106.05(b)), the claims do not effect a transformation or reduction of a particular article to a different state or thing (MPEP 2106.05(c)), and the claims do not apply or use the abstract idea in some other meaningful way beyond generally linking the use of the abstract idea to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception (MPEP 2106.05(e) and Vanda Memo). Therefore, the claims do not, for example, purport to improve the functioning of a computer. Nor do they effect an improvement in any other technology or technical field. Accordingly, the additional elements do not impose any meaningful limits on practicing the abstract idea, and the claims are directed to an abstract idea.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because, when analyzed under step 2B of the Alice/Mayo test (See 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50, 52, 56 (January 7, 2019)), the additional element(s) of using a memory and a processor to perform the steps amounts to no more than using a computer or processor to automate and/or implement the abstract idea of deriving virtual address via offsets. As discussed above, taking the claim elements separately, the memory and a processor perform(s) the steps or functions of receiving an instruction for performing a collective operation across at least one processing element, wherein the instruction specifies a first virtual address that is included in a first set of contiguous virtual addresses for unicast operations. These functions correspond to the actions required to perform the abstract idea. Viewed as a whole, the combination of elements recited in the claims merely recite the concept of deriving virtual address via offsets. Therefore, the use of these additional elements does no more than employ the computer as a tool to automate and/or implement the abstract idea. The use of a computer or processor to merely automate and/or implement the abstract idea cannot provide significantly more than the abstract idea itself (MPEP 2106.05(I)(A)(f) & (h)). Therefore, the claim is not patent eligible.
Dependent claims 3-10, 12-19 further describe the abstract idea of deriving virtual address via offsets. The dependent claims do not include additional elements that integrate the abstract idea into a practical application or that provide significantly more than the abstract idea. Therefore, the dependent claims are also not patent eligible.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1,11, and 20, the limitation “wherein the at least one processing element is associated with the first set of contiguous virtual addresses and the second set of contiguous virtual addresses, and wherein the first set of contiguous virtual addresses and the second set of contiguous virtual addresses are respectively symmetric” is unclear because it not know if each set of virtual addresses are independently symmetric or if the two sets are symmetric relative to each other.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shapiro (U.S. Patent 8407377) in view of Arunachalam (U.S. Patent App Pub 20230195613).
Regarding claim 1,
Shapiro teaches a method, comprising: receiving an instruction for performing a collective operation across at least one processing element, wherein the instruction specifies a first virtual address that is included in a first set of contiguous virtual addresses for unicast operations; (See column 14 lines 3-37, Shapiro)
determining an offset of the first virtual address from a first base address associated with the first set of contiguous virtual addresses; (See column 8 lines 20-57, and figures 2-4, Shapiro)
translating the first virtual address to a corresponding multicast virtual address based on the offset, wherein the multicast virtual address is included in a second set of contiguous virtual addresses for multicast operations, and wherein the multicast virtual address is located at the offset from a second base address associated with the second set of contiguous virtual addresses; and (See column 6 lines 5-37, and figures 2-4, Shapiro)
causing the collective operation to be performed based at least on the multicast virtual address. (See column 8 lines 20-57, and figures 2-4, Shapiro)
Shapiro does not explicitly teach but Arunachalam teaches wherein the at least one processing element is associated with the first set of contiguous virtual addresses and the second set of contiguous virtual addresses, and wherein the first set of contiguous virtual addresses and the second set of contiguous virtual addresses are respectively symmetric. (See paragraphs 20-23, Arunachalam)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have known to combine the teachings of Arunachalam with Shapiro because both deal with virtual addressing. The advantage of incorporating the above limitation(s) of Arunachalam into Shapiro is that Arunachalam enables utilizing a virtual memory space to allow a computer system to have a relatively smaller physical memory space by swapping data between physical memory and secondary storage in effective manner, and allocating and managing the memory for large scale memory requestors in efficient manner, therefore making the overall system more robust and efficient. (See paragraphs [0011] - [0013], Arunachalam)
Regarding claim 3,
Shapiro and Arunachalam teach the method of claim 2, further comprising, for a given processing element of the at least one processing unit, binding a virtual address in the first set of contiguous virtual addresses to a first physical address in a physical memory space associated with the given processing element, wherein a virtual address in the second set of contiguous virtual addresses that is located at a same offset as the virtual address in the first set of contiguous virtual addresses is bound the first physical address. (See column 9 lines 5-63, Shapiro)
Regarding claim 4,
Shapiro and Arunachalam teach the method of claim 3, wherein the virtual address in the first set of contiguous virtual addresses is located at a current offset from the first base virtual address and the virtual address in the second set of contiguous virtual addresses is located at the current offset from the second base virtual address. (See column 9 lines 5-63, Shapiro)
Regarding claim 5,
Shapiro and Arunachalam teach the method of claim 1, wherein the collective operation is performed, at least in part, within a switch coupled to the at least one processing element. (See column 9 line 50 – column 10 line 7, Shapiro)
Regarding claim 6,
Shapiro and Arunachalam teach the method of claim 1, further comprising determining that the first virtual address is to be translated to the multicast virtual address based on a type of operation associated with the collective operation. (See column 14 lines 3-45, Shapiro)
Regarding claim 7,
Shapiro and Arunachalam teach the method of claim 1, wherein the instruction is received for a central processing unit coupled to the at least one processing element, and wherein the translating the first virtual address to the corresponding multicast virtual address occurs within the at least one processing element. (See column 9 lines 5-63, Shapiro)
Regarding claim 8,
Shapiro and Arunachalam teach the method of claim 1, wherein the translating the first virtual address to the corresponding multicast virtual address is an O(1) operation. (See column 9 lines 5-63, Shapiro)
Regarding claim 9,
Shapiro and Arunachalam teach the method of claim 1, wherein the collective operation is performed across the at least one processing element based on data stored in the multicast virtual address corresponding to the at least one processing element. (See column 9 line 50 – column 10 line 7, Shapiro)
Regarding claim 10,
Shapiro and Arunachalam teach the method of claim 1, wherein at least a partial result of the collective operation is stored in the multicast virtual address corresponding to the at least one processing element. (See column 6 lines 37-65, Shapiro)
Claims 11-19 list all the same elements of claims 1,3-4, 6-10, but in system form rather than method form. Therefore, the supporting rationale of the rejection to claims 1, 3-4, 6-10 applies equally as well to claims 11-19.
Regarding claim 20,
Shapiro teaches at least one processor, comprising: processing circuitry to cause a collective operation to be performed across at least one processing unit based at least on a first virtual address of a first type determined from at least an offset of a corresponding virtual address of a second type in a second set of contiguous virtual addresses for operations associated with the second type. (See column 8 lines 35-50, col 9 lines 4-33, Shapiro)
Shapiro does not explicitly teach but Arunachalam teaches wherein the at least one processing element is associated with the first set of contiguous virtual addresses and the second set of contiguous virtual addresses, and wherein the first set of contiguous virtual addresses and the second set of contiguous virtual addresses are respectively symmetric. (See paragraphs 20-23, Arunachalam)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have known to combine the teachings of Arunachalam with Shapiro because both deal with virtual addressing. The advantage of incorporating the above limitation(s) of Arunachalam into Shapiro is that Arunachalam enables utilizing a virtual memory space to allow a computer system to have a relatively smaller physical memory space by swapping data between physical memory and secondary storage in effective manner, and allocating and managing the memory for large scale memory requestors in efficient manner, therefore making the overall system more robust and efficient. (See paragraphs [0011] - [0013], Arunachalam)
Response to Arguments
Applicant's arguments filed 5/12/2026 have been fully considered but they are not persuasive.
A. Applicant argues that the claims are not directed to a judicial exception under Step 2A Prong One. As for Step 2A Prong One, of the Abstract idea is directed towards the abstract idea of deriving virtual address via offsets which is grouped within the Methods Of Organizing Human Activity and is similar to the concept of (fundamental economic principles or practices including hedging insurance, mitigating risk) OR (commercial or legal interactions including agreements in the form of contracts, legal obligations, advertising, marketing or sales activities or behaviors business relations) OR (managing personal behavior or relationships or interactions between people including social activities teaching, and following rules or instructions) OR Mental Processes and is similar to the concept of (concepts performed in the human mind (including an observation, evaluation, judgement, opinion) grouping of abstract ideas in prong one of step 2A of the Alice/Mayo test (See 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50, 52, 54 (January 7, 2019)). Accordingly, the claims recite an abstract idea (See pages 7, 10, Alice Corporation Pty. Ltd. v. CLS Bank International, et al., US Supreme Court, No. 13-298, June 19, 2014; 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50, 53-54 (January 7, 2019)).
B. Applicant argues that the claims are not directed to a judicial exception under Step 2A Prong Two. As for Step 2A Prong Two, the claim limitations do not include additional elements in the claim that apply, rely on, or use the judicial exception in a manner that imposes a meaningful limit on the judicial exception, and the claim is not more than a drafting effort designed to monopolize the judicial exception and the claim limitation simply describe the abstract idea. The limitation directed to deriving virtual address via offsets does not add technical improvement to the abstract idea. The recitations to memory and a processor perform(s) the steps or functions of receiving an instruction for performing a collective operation across at least one processing element, wherein the instruction specifies a first virtual address that is included in a first set of contiguous virtual addresses for unicast operations. The use of a processor/computer as a tool to implement the abstract idea and/or generally linking the use of the abstract idea to a particular technological environment does not integrate the abstract idea into a practical application because it requires no more than a computer performing functions that correspond to acts required to carry out the abstract idea. The additional elements do not involve improvements to the functioning of a computer, or to any other technology or technical field (MPEP 2106.05(a)), the claims do not apply or use the abstract idea to effect a particular treatment or prophylaxis for a disease or medical condition (Vanda Memo), the claims do not apply the abstract idea with, or by use of, a particular machine (MPEP 2106.05(b)), the claims do not effect a transformation or reduction of a particular article to a different state or thing (MPEP 2106.05(c)), and the claims do not apply or use the abstract idea in some other meaningful way beyond generally linking the use of the abstract idea to a particular technological environment, such that the claim as a whole is more than a drafting effort designed to monopolize the exception (MPEP 2106.05(e) and Vanda Memo). Therefore, the claims do not, for example, purport to improve the functioning of a computer. Nor do they effect an improvement in any other technology or technical field. Accordingly, the additional elements do not impose any meaningful limits on practicing the abstract idea, and the claims are directed to an abstract idea.
C. Applicant argues that the claims are not directed to a judicial exception under Step 2B.
As for Step 2B, The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because, when analyzed under step 2B of the Alice/Mayo test (See 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50, 52, 56 (January 7, 2019)), the limitation directed to deriving virtual address via offsets does not add significantly more to the abstract idea. Furthermore, using well-known computer functions to execute an abstract idea does not constitute significantly more. The recitations to memory and a processor are generically recited computer structure. These functions correspond to the actions required to perform the abstract idea. Viewed as a whole, the combination of elements recited in the claims merely recite the concept of deriving virtual address via offsets. Therefore, the use of these additional elements does no more than employ the computer as a tool to automate and/or implement the abstract idea. The use of a computer or processor to merely automate and/or implement the abstract idea cannot provide significantly more than the abstract idea itself (MPEP 2106.05(I)(A)(f) & (h)). Therefore, the claim is not patent eligible.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and located in the PTO-892 form.
1.Kamata, U.S. Patent App 20070171930, teaches an IPv4-IPv6 multicast address translation table is dynamically created, so that it is unnecessary to register multicast servers in advance. When an IPv4 MC group address exists as a response of a DNS server to a DNS request of an IPv6 MC client or when an IPv6 MC group address exists as a response of the DNS server to a DNS request of the IPv4 MC client H1 to H4, DNS Proxy D3 requests an MC adaptive translator T1 to generate a virtual IPv6 MC group address or a virtual IPv4 MC group address, and the MC adaptive
translator T1 generates a virtual IPv6 MC group address or a virtual IPv4 MC group address from an address pool, and also creates an MC address translation table, whereby the MC address translation of IPv4-IPv6 can be dynamically performed.
2. Cheriton, U.S. Patent App 20050089050, teaches a method for using network address translation in switches and routers to define a virtual host as the source of a multicast channel within a single-source multicast model and to translate packet addresses from different multicast sources so that the packets appear to be originating from the virtual host. Address-translated packets are thus forwarded through a single-source multicast channel and received by the subscribing host(s)/clients as though the packets came from a single "virtual" source. This methodology can be used to map two or more sources simultaneously onto the same multicast channel. Such a mapping is useful, for example, to present multiple views of a sporting event video broadcast, provide advertisement insertion capability, or to support transparent fail-over to a backup video source in a critical multicast application. Subscribing client hosts in the multicast reception group simply subscribe to the single virtual host as the source of a multicast channel.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NINOS DONABED/Primary Examiner, Art Unit 2444
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