DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on October 17, 2024 refers to foreign and non-patent references that were submitted in relation to a similar IDS filed for Application No. 15/314,316 (an antecedent case to the current Application). Since the records of antecedent cases are incorporated by reference, this appears to satisfy the requirement for corresponding documentation.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: DQs, DQp, CAs, CAp, tCK, tWRP, CA-Prow, CA-Pcol, CA-Srow, CA-Scol, DQ-P, DQ-S.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 5-6, 8, 15, and 19-20 are objected to because of the following informalities:
In claim 5, line 2, “interface to dispatch” should be -interface dispatches-.
In claim 8, line 5, “condition;” should be -condition; and wherein-
In claim 8, line 7, “to transition” should be -transitions-.
In claim 8, line 8, “to dispatch” should be -dispatches-.
In claim 8, line 10, “to receive” should be -receives-.
In claim 15, line 10, “to receiving” should be -receiving-.
In claim 19, line 2, “to dispatch” should be -dispatches-.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-4 and 7-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-10, 12, and 14 of U.S. Patent No. 10,628,348.
Current claims 2-4 and 7-8
Claims 8-10, 12, and 14, ‘348 patent
2. An integrated circuit (IC) memory controller, comprising: a command interface to dispatch first write command information for writing first data to a memory device;
8. The IC memory controller according to claim 2, further comprising: bus interface circuitry to transition a bus interface to a write condition;
8. A memory controller, comprising: a bus interface, bus interface logic to transition the bus interface to a write condition; command logic to dispatch a write command for writing first data to a memory device;
8. (continued) data interface circuitry to transmit the first data associated with the first write command information via the bus interface to the memory device while the bus interface is in the write condition;
data interface circuitry to transmit write data associated with the write command via the bus interface to the memory device while the bus interface is in the write condition;
8. (continued) during the queuing interval time duration, the bus interface circuitry to transition the bus interface to a read condition;
during a queuing interval, the bus interface logic to transition the bus interface to a read condition;
8. (continued) the command interface to dispatch a read command for reading second data from the memory device; and
the command logic to dispatch a read command for reading second data from the memory device; and
8. (continued) the data interface circuitry to receive the second data from the memory device via the bus interface while the bus interface is in the read condition.
the data interface circuitry to receive the second data from the memory device via the bus interface while the bus interface is in the read condition; and
2. (continued) wherein the first write command information comprises a value specified in a mode field, the value corresponding to a queuing interval time duration to queue the first data before writing the first data to the memory device.
wherein the queuing interval comprises a time duration during which the first data is queued prior to being written to the memory device.
3. The IC memory controller according to claim 2, wherein: the queuing interval time duration corresponds to a bank cycle interval.
9. The memory controller according to claim 8, wherein: the queuing interval time duration corresponds to a bank cycle interval.
4. The IC memory controller according to claim 3, wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the memory device.
10. The memory controller according to claim 9, wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the memory device.
12. The memory controller according to claim 9, wherein: the bank cycle interval corresponds to a value specified in a mode field associated with the write command.
7. The IC memory controller according to claim 2, embodied as a dynamic random access memory (DRAM) controller.
14. The memory controller according to claim 8, embodied as a dynamic random access memory (DRAM) controller.
Both the current independent claim 2 and independent claim 8 of the ‘348 patent disclose a memory controller, comprising: a command interface to dispatch first write command information for writing first data to a memory device, and a queuing interval time duration to queue the first data before writing the first data to the memory device.
Both the current claim 8 and claim 8 of the ‘348 patent disclose bus interface circuitry to transition a bus interface to a write condition; data interface circuitry to transmit the first data associated with the first write command information via the bus interface to the memory device while the bus interface is in the write condition; during the queuing interval time duration, the bus interface circuitry to transition the bus interface to a read condition; the command interface to dispatch a read command for reading second data from the memory device; and the data interface circuitry to receive the second data from the memory device via the bus interface while the bus interface is in the read condition.
Both the current claim 2 and claim 12 of the ‘348 patent disclose wherein: the bank cycle interval corresponds to a value specified in a mode field associated with the write command.
The current claim 2 further clarifies that the memory controller is an IC memory controller, while the corresponding claims of the ‘348 patent do not explicitly disclose this. However, it is respectfully submitted that implementing a memory controller as an integrated circuit is a known embodiment, and would not require undue experimentation to implement.
Based on this, current claims 2 and 8 are rejected on the ground of nonstatutory obviousness-type double patenting.
Both the current claim 3 and claim 9 of the ‘348 patent disclose wherein: the queuing interval time duration corresponds to a bank cycle interval.
Both the current claim 4 and claim 10 of the ‘348 patent disclose wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the memory device.
Both the current claim 7 and claim 14 of the ‘348 patent disclose the memory controller embodied as a dynamic random access memory (DRAM) controller.
Based on these disclosures and the disclosures of their respective antecedent claims, claims 3-4 and 7 are rejected on the ground of nonstatutory obviousness-type double patenting.
Claims 9-11 and 14-15 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5, and 7 of the ‘348 patent in view of claim 8 of the ‘348 patent.
Claims 9-11 and 14-15, current application
Claims 1-3, 5, and 7-8, ‘348 patent
9. A method of operation for a memory controller, comprising: dispatching, via a command interface, first write command information for writing first data to a memory device;
15. The method according to claim 9, further comprising: transitioning, with bus interface circuitry, a bus interface to a write condition;
1. A method of operation for a memory controller, comprising: transitioning a bus interface to a write condition; dispatching a write command for writing first data to a memory device;
8. A memory controller, comprising: a bus interface, bus interface logic to transition the bus interface to a write condition; command logic to dispatch a write command for writing first data to a memory device;
15. (continued) transmitting, with data interface circuitry, the first data associated with the first write command information via the bus interface to the memory device while the bus interface is in the write condition;
1. (continued) transmitting write data associated with the write command via the bus interface to the memory device while the bus interface is in the write condition;
8. (continued) data interface circuitry to transmit write data associated with the write command via the bus interface to the memory device while the bus interface is in the write condition;
15. (continued) during the queuing interval time duration, transitioning the bus interface to a read condition;
1. (continued) during a queuing interval, transitioning the bus interface to a read condition;
15. (continued) dispatching, with the command interface, a read command for reading second data from the memory device; and
1. (continued) dispatching a read command for reading second data from the memory device; and
15. (continued) the data interface circuitry to receiving, with the data interface circuitry, the second data from the memory device via the bus interface while the bus interface is in the read condition.
1. (continued) receiving the second data from the memory device via the bus interface while the bus interface is in the read condition; and
9. (continued) wherein the first write command information comprises a value specified in a mode field, the value corresponding to a queuing interval time duration to queue the first data before writing the first data to the memory device.
1. (continued) wherein the queuing interval comprises a time duration during which the first data is queued prior to being written to the memory device.
10. The method according to claim 9, wherein: the queuing interval time duration corresponds to a bank cycle interval.
2. The method according to claim 1, wherein: the queuing interval time duration corresponds to a bank cycle interval.
11. The method according to claim 10, wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the memory device.
3. The method according to claim 2, wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the memory device.
5. The method according to claim 2, wherein: the bank cycle interval corresponds to a value specified in a mode field associated with the write command.
14. The method according to claim 9, embodied as a dynamic random access memory (DRAM) protocol.
7. The method according to claim 1, wherein: the transitioning of the bus interface, the dispatching of the write command, and the transmitting write data is carried out via a dynamic random access memory (DRAM) protocol.
Both the current claim 9 and claim 1 of the ‘348 patent disclose a method of operation for a memory controller, comprising: dispatching first write command information for writing first data to a memory device, wherein a queuing interval comprises a time duration during which the first data is queued prior to being written to the memory device.
Both the current claim 15 and claim 1 of the ‘348 patent disclose transitioning a bus interface to a write condition; transmitting write data associated with the write command via the bus interface to the memory device while the bus interface is in the write condition; during a queuing interval, transitioning the bus interface to a read condition; dispatching a read command for reading second data from the memory device; and receiving the second data from the memory device via the bus interface while the bus interface is in the read condition.
Both the current claim 9 and claim 5 of the ‘348 patent disclose wherein: the bank cycle interval corresponds to a value specified in a mode field associated with the write command.
Current claim 9 further discloses that a command interface dispatches the write command information.
Current claim 15 further discloses that the bus interface performs the transitioning step, data interface circuitry transmits write data, and the command interface further dispatches read command information.
While claim 1 of the ‘348 patent does not appear to disclose this, claim 8 of the ‘348 patent, as shown above, does disclose “bus interface logic to transition the bus interface to a write condition”, “data interface circuitry to transmit write data associated with the write command via the bus interface to the memory device while the bus interface is in the write condition”, and “the command logic to dispatch a read command for reading second data from the memory device”.
Based on this, it is determined that it would have been known to use bus interface logic to transition a bus interface to a write condition, data interface circuitry to transmit write data associated with the write command via the bus interface to the memory device while the bus interface is in the write condition, and command logic to dispatch a read command for reading second data from the memory device.
Therefore, current claims 9 and 15 are rejected on the ground of nonstatutory obviousness-type double patenting.
Both the current claim 10 and claim 2 disclose wherein: the queuing interval time duration corresponds to a bank cycle interval.
Both the current claim 11 and claim 3 disclose wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the memory device.
Both the current claim 14 and claim 7 disclose the method embodied as a dynamic random access memory (DRAM) protocol.
Based on this, claims 10-11 and 14 are likewise rejected based on nonstatutory obviousness-type double patenting.
Claims 16-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15-17 and 19 of the ‘348 patent. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the ‘348 patent anticipate the current claims.
Current claims 16-18
Claims 15-17 and 19, ‘348 patent
16. An integrated circuit (IC) chip, comprising: memory control circuitry comprising: a command interface to dispatch first write command information for writing data to an IC memory device;
15. An integrated circuit (IC) memory controller chip, comprising: interface circuitry to transition a bus interface to a write condition; command logic to dispatch a write command for writing first data to a memory device;
15 (continued) the interface circuitry to transmit write data associated with the write command via the bus interface to the memory device while the bus interface is in the write condition;
15. (continued) during a queuing interval, the interface circuitry to transition the bus interface to a read condition;
15. (continued) the command logic to dispatch a read command for reading second data from the memory device; and
15. (continued) the interface circuitry to receive the second data from the memory device via the bus interface while the bus interface is in the read condition; and
16. (continued) wherein the first write command information comprises a value specified in a mode field, the value corresponding to a queuing interval time duration to queue the data before writing the data to the IC memory device.
15. (continued) wherein the queuing interval comprises a time duration during which the first data is queued prior to being written to the memory device.
17. The IC chip according to claim 16, wherein: the queuing interval time duration corresponds to a bank cycle interval.
16. The IC memory controller chip according to claim 15, wherein: the queuing interval time duration corresponds to a bank cycle interval.
18. The IC chip according to claim 17, wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the IC memory device.
17. The IC memory controller chip according to claim 16, wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the memory device.
19. The IC memory controller chip according to claim 16, wherein: the bank cycle interval corresponds to a value specified in a mode field associated with the write command.
Both the current claim 16 and claim 15 of the ‘348 patent disclose an integrated circuit chip comprising: memory control circuitry comprising: a command interface to dispatch first write command information for writing data to an IC memory device; wherein the first write command information comprises a time duration to queue the data before writing the data to the IC memory device.
Both the current claim 16 and claim 19 of the ‘348 patent disclose wherein: the bank cycle interval corresponds to a value specified in a mode field associated with the write command.
As shown, claim 15 of the ‘348 patent has further disclosures which are not included in the current claim 16. Based on this, claim 15 of the ‘348 patent appears to anticipate the current claim 16.
Therefore, the current claim 16 is rejected on the ground of nonstatutory anticipation-type double patenting.
As shown, current claims 17 and 18 appear to be anticipated by claims 16 and 17 of the ‘348 patent. Therefore, claims 17 and 18 are rejected on the ground of nonstatutory anticipation-type double patenting.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2, 5-6, 9, 12-13, 16, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (US 7,246,250), hereafter referred to as Jung’250.
Referring to independent claim 2, Jung’250 anticipates an integrated circuit (IC) memory controller, comprising: a command interface to dispatch first write command information for writing first data to a memory device (command output buffer 411, see figure 4 and column 4, lines 34-35; generate a command signal COM, column 4, line 41); wherein the first write command information comprises a value specified in a mode field (delay control information contained in delay control register 400, see figure 4 and column 4, lines 43-45), the value corresponding to a queuing interval time duration to queue the first data before writing the first data to the memory device (delay controller 417 generates an output signal specifying a delay time in response to the delay control information contained in the delay control register 400 and the module selection signal MODS2, see figure 4 and column 4, lines 46-49; data output buffer 415 delays write data DATI in response to output signal of delay controller 417 and module selection signal MODS1, see figure 4 and column 4, lines 55-58).
Note that independent claims 9 and 16 contain the corresponding limitations of claim 2 as shown above; therefore, they are rejected using the same reasoning accordingly.
As to claim 5, Jung’250 anticipates the IC memory controller according to claim 2, wherein: the command interface dispatches the first write command information to the memory device via a queuing circuit that is attached to the memory device (output buffer 410 comprises command output buffer 411, see figure 4 and column 4, lines 34-36); and wherein the queuing circuit temporarily stores the first data during the queuing interval time duration (data output buffer 415 delays write data DATI in response to output signal of delay controller 417 and module selection signal MODS1, see figure 4 and column 4, lines 55-58).
Note that claims 12 and 19 contain the corresponding limitations of claim 5 as shown above; therefore, they are rejected using the same reasoning accordingly.
As to claim 6, Jung’250 anticipates the IC memory controller according to claim 5, wherein: the queuing circuit comprises an IC buffer circuit (data output buffer 415 delays write data DATI in response to output signal of delay controller 417 and module selection signal MODS1, see figure 4 and column 4, lines 55-58) that is attached to the memory device (signals transmitted between the memory controller and the memory modules 110, 130, and 150, see figure 3 and column 6, lines 7-8).
Note that claims 14 and 20 contain the corresponding limitations of claim 6 as shown above; therefore, they are rejected using the same reasoning accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-4, 7, 10-11, 14, 17-18, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung’250 in view of Singh et al. (US 2007/0011396), hereafter referred to as Singh’396.
As to claim 3, Jung’250 does not appear to explicitly teach the IC memory controller according to claim 2, wherein: the queuing interval time duration corresponds to a bank cycle interval.
However, Singh’396 teaches wherein the queuing interval time duration corresponds to a bank cycle interval (access patterns that can lead to lost cycles are: access to the bank adjacent to the current activated bank, access to the same bank as the current activated bank but on a different device, and access to a different row than the current accessed row on the current activated bank, paragraph 8, lines 17-22).
Jung’250 and Singh’396 are analogous because they are both drawn to the same inventive field of memory buffers.
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung’250 and Singh’396 before them, to modify the IC memory controller of Jung’250 to include the cycle interval of Singh’396 by setting the buffer delays of Jung’250 to correspond to “lost cycles” of Singh’396.
The motivation for doing so would have been to provide an optimized scheduling scheme that avoids scheduling conflicts to increase memory channel efficiency and mitigate the effects associated with a high DRAM read latency (paragraph 10, lines 9-13).
Therefore, it would have been obvious to combine Jung’250 and Singh’396 to bring about the invention as claimed.
Note that claims 10 and 17 contain the corresponding limitations of claim 3 as shown above; therefore, they are rejected using the same reasoning accordingly.
As to claim 4, Jung’250 does not appear to explicitly teach the IC memory controller according to claim 3, wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the memory device.
However, Singh’396 teaches wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the memory device (access patterns that can lead to lost cycles are: access to the bank adjacent to the current activated bank, access to the same bank as the current activated bank but on a different device, and access to a different row than the current accessed row on the current activated bank, paragraph 8, lines 17-22).
Jung’250 and Singh’396 are analogous because they are both drawn to the same inventive field of memory buffers.
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung’250 and Singh’396 before them, to modify the IC memory controller of Jung’250 to include the cycle interval of Singh’396 by setting the buffer delays of Jung’250 to correspond to “lost cycles” of Singh’396.
The motivation for doing so would have been to provide an optimized scheduling scheme that avoids scheduling conflicts to increase memory channel efficiency and mitigate the effects associated with a high DRAM read latency (paragraph 10, lines 9-13).
Therefore, it would have been obvious to combine Jung’250 and Singh’396 to bring about the invention as claimed.
Note that claims 11 and 18 contain the corresponding limitations of claim 4 as shown above; therefore, they are rejected using the same reasoning accordingly.
As to claim 7, Jung’250 does not appear to explicitly teach the IC memory controller according to claim 2, embodied as a dynamic random access memory (DRAM) controller.
However, Singh’396 teaches a dynamic random access memory controller (DRAM controller, paragraph 23, lines 11-12).
Jung’250 and Singh’396 are analogous because they are both drawn to the same inventive field of memory buffers.
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung’250 and Singh’396 before them, to modify the IC memory controller of Jung’250 to include a DRAM controller as in Singh’396 by implementing the controller as a DRAM controller.
The motivation for doing so would have been to provide an optimized scheduling scheme that avoids scheduling conflicts to increase memory channel efficiency and mitigate the effects associated with a high DRAM read latency (paragraph 10, lines 9-13).
Therefore, it would have been obvious to combine Jung’250 and Singh’396 to bring about the invention as claimed.
Note that claims 14 and 21 contain the corresponding limitations of claim 7 as shown above; therefore, they are rejected using the same reasoning accordingly.
Allowable Subject Matter
Claims 8 and 15 appear to contain allowable subject matter; however, they cannot be allowed at this time due to depending on a rejected claim, as well as the double patenting rejection on these claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 8, the prior art of record does not appear to anticipate or explicitly teach wherein, during the queuing interval time duration, the bus interface circuitry transitions the bus interface to a read condition.
Further, it would not have been obvious to combine the above limitation with the remaining limitations of the claim, or of the antecedent claim.
Ware et al. (US 2012/0179880) discloses transfer of data during a bank cycle interval. However, this does not appear to anticipate or explicitly teach transitioning the bus interface during such an interval.
Note that claim 15 contains the corresponding limitations of claim 8 as shown above; therefore, it is considered to contain allowable subject matter based on the same reasoning accordingly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ware et al. (US 2012/0179880) discloses transfer of data during a bank cycle interval.
However, these references do not appear to anticipate or explicitly teach the subject matter determined to be allowable.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN B ROCHE whose telephone number is (571)270-1721. The examiner can normally be reached Monday-Friday, 10:30 - 7.
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/J.B.R/Examiner, Art Unit 2184
/STEVEN G SNYDER/Primary Examiner, Art Unit 2184