DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendments to the Drawings submitted June 23, 2026, appear to overcome the Objections to the Drawings in the previous Office Action. Therefore, the Objections to the Drawings in the previous Office Action are withdrawn.
The Amendments to the Claims submitted June 23, 2026, appear to overcome the Objections to the Claims in the previous Office Action. Therefore, the Objections to the Claims in the previous Office Action are withdrawn.
Double Patenting
Claims 2-4 and 7-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-10, 12, and 14 of U.S. Patent No. 10,628,348.
Claims 9-11 and 14-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5, and 7 of the ‘348 patent in view of claim 8 of the ‘348 patent.
The rejections on the ground of nonstatutory double patenting were provided in detail in the previous Office Action. Since these rejections are already on record, for the sake of brevity they are not repeated here.
The Applicant has declared an intention to submit an eTerminal Disclaimer in response to this rejection. No such disclaimer appears to have been received by the Office at this time.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2, 5-6, 9, 12-13, 16, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (US 7,246,250), hereafter referred to as Jung’250.
Referring to independent claim 2, Jung’250 anticipates an integrated circuit (IC) memory controller, comprising: a command interface to dispatch first write command information for writing first data to a memory device (command output buffer 411, see figure 4 and column 4, lines 34-35; generate a command signal COM, column 4, line 41); wherein the first write command information comprises a value specified in a mode field (delay control information contained in delay control register 400, see figure 4 and column 4, lines 43-45), the value corresponding to a queuing interval time duration to queue the first data before writing the first data to the memory device (delay controller 417 generates an output signal specifying a delay time in response to the delay control information contained in the delay control register 400 and the module selection signal MODS2, see figure 4 and column 4, lines 46-49; data output buffer 415 delays write data DATI in response to output signal of delay controller 417 and module selection signal MODS1, see figure 4 and column 4, lines 55-58).
Note that independent claims 9 and 16 contain the corresponding limitations of claim 2 as shown above; therefore, they are rejected using the same reasoning accordingly.
As to claim 5, Jung’250 anticipates the IC memory controller according to claim 2, wherein: the command interface dispatches the first write command information to the memory device via a queuing circuit that is attached to the memory device (output buffer 410 comprises command output buffer 411, see figure 4 and column 4, lines 34-36); and wherein the queuing circuit temporarily stores the first data during the queuing interval time duration (data output buffer 415 delays write data DATI in response to output signal of delay controller 417 and module selection signal MODS1, see figure 4 and column 4, lines 55-58).
Note that claims 12 and 19 contain the corresponding limitations of claim 5 as shown above; therefore, they are rejected using the same reasoning accordingly.
As to claim 6, Jung’250 anticipates the IC memory controller according to claim 5, wherein: the queuing circuit comprises an IC buffer circuit (data output buffer 415 delays write data DATI in response to output signal of delay controller 417 and module selection signal MODS1, see figure 4 and column 4, lines 55-58) that is attached to the memory device (signals transmitted between the memory controller and the memory modules 110, 130, and 150, see figure 3 and column 6, lines 7-8).
Note that claims 13 and 20 contain the corresponding limitations of claim 6 as shown above; therefore, they are rejected using the same reasoning accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3-4, 7, 10-11, 14, 17-18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Jung’250 in view of Singh et al. (US 2007/0011396), hereafter referred to as Singh’396.
As to claim 3, Jung’250 does not appear to explicitly teach the IC memory controller according to claim 2, wherein: the queuing interval time duration corresponds to a bank cycle interval.
However, Singh’396 teaches wherein the queuing interval time duration corresponds to a bank cycle interval (access patterns that can lead to lost cycles are: access to the bank adjacent to the current activated bank, access to the same bank as the current activated bank but on a different device, and access to a different row than the current accessed row on the current activated bank, paragraph 8, lines 17-22).
Jung’250 and Singh’396 are analogous because they are both drawn to the same inventive field of memory buffers.
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung’250 and Singh’396 before them, to modify the IC memory controller of Jung’250 to include the cycle interval of Singh’396 by setting the buffer delays of Jung’250 to correspond to “lost cycles” of Singh’396.
The motivation for doing so would have been to provide an optimized scheduling scheme that avoids scheduling conflicts to increase memory channel efficiency and mitigate the effects associated with a high DRAM read latency (paragraph 10, lines 9-13).
Therefore, it would have been obvious to combine Jung’250 and Singh’396 to bring about the invention as claimed.
Note that claims 10 and 17 contain the corresponding limitations of claim 3 as shown above; therefore, they are rejected using the same reasoning accordingly.
As to claim 4, Jung’250 does not appear to explicitly teach the IC memory controller according to claim 3, wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the memory device.
However, Singh’396 teaches wherein: the bank cycle interval represents a minimum time delay between successive accesses to rows within different banks of the memory device (access patterns that can lead to lost cycles are: access to the bank adjacent to the current activated bank, access to the same bank as the current activated bank but on a different device, and access to a different row than the current accessed row on the current activated bank, paragraph 8, lines 17-22).
Jung’250 and Singh’396 are analogous because they are both drawn to the same inventive field of memory buffers.
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung’250 and Singh’396 before them, to modify the IC memory controller of Jung’250 to include the cycle interval of Singh’396 by setting the buffer delays of Jung’250 to correspond to “lost cycles” of Singh’396.
The motivation for doing so would have been to provide an optimized scheduling scheme that avoids scheduling conflicts to increase memory channel efficiency and mitigate the effects associated with a high DRAM read latency (paragraph 10, lines 9-13).
Therefore, it would have been obvious to combine Jung’250 and Singh’396 to bring about the invention as claimed.
Note that claims 11 and 18 contain the corresponding limitations of claim 4 as shown above; therefore, they are rejected using the same reasoning accordingly.
As to claim 7, Jung’250 does not appear to explicitly teach the IC memory controller according to claim 2, embodied as a dynamic random-access memory (DRAM) controller.
However, Singh’396 teaches a dynamic random access memory controller (DRAM controller, paragraph 23, lines 11-12).
Jung’250 and Singh’396 are analogous because they are both drawn to the same inventive field of memory buffers.
Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung’250 and Singh’396 before them, to modify the IC memory controller of Jung’250 to include a DRAM controller as in Singh’396 by implementing the controller as a DRAM controller.
The motivation for doing so would have been to provide an optimized scheduling scheme that avoids scheduling conflicts to increase memory channel efficiency and mitigate the effects associated with a high DRAM read latency (paragraph 10, lines 9-13).
Therefore, it would have been obvious to combine Jung’250 and Singh’396 to bring about the invention as claimed.
Note that claims 14 and 21 contain the corresponding limitations of claim 7 as shown above; therefore, they are rejected using the same reasoning accordingly.
Allowable Subject Matter
Claims 8 and 15 appear to contain allowable subject matter; however, they cannot be allowed at this time due to depending on a rejected claim, as well as the double patenting rejection on these claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 8, the prior art of record does not appear to anticipate or explicitly teach wherein, during the queuing interval time duration, the bus interface circuitry transitions the bus interface to a read condition.
Further, it would not have been obvious to combine the above limitation with the remaining limitations of the claim, or of the antecedent claim.
Ware et al. (US 2012/0179880) discloses transfer of data during a bank cycle interval. However, this does not appear to anticipate or explicitly teach transitioning the bus interface during such an interval.
Note that claim 15 contains the corresponding limitations of claim 8 as shown above; therefore, it is considered to contain allowable subject matter based on the same reasoning accordingly.
Response to Arguments
Applicant's arguments filed June 23, 2026, have been fully considered but they are not persuasive.
Referring to independent claim 2, the Applicant argues that Jung’250 does not anticipate wherein the first write command information comprises a value specified in a mode field, arguing that the value that is stored in the delay control register of Jung’250 is not part of "first write command information" as claimed (page 9, lines 10-20).
The Examiner respectfully submits that the delay control register governs the delay time specified by the delay controller, and that this delay signal affects command signals by the command output buffer, as shown in column 4 of Jung’250, lines 46-52. Based on this, it is respectfully submitted that the delay control register-influenced delay time anticipates the value in a mode field of the write command information.
As to independent claims 9 and 16, the Applicant argues that they are distinguished over Jung by the same reasoning as claim 2. The Examiner therefore applies the response to the arguments regarding claim 2 to these arguments accordingly.
As to claims 5-6, 12-13, and 19-20, the Applicant argues that they are distinguished over Jung by the same reasoning as claim 2. The Examiner therefore applies the response to the arguments regarding claim 2 to these arguments accordingly.
As to claims 3-4, 7, 10-11, 14, 17-18, and 21, the Applicant argues that they are patentable over Jung and Singh for at least the reasons that apply to the independent claims. The Examiner therefore applies the response to the arguments regarding claim 2 to these arguments accordingly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ware et al. (US 2012/0179880) discloses transfer of data during a bank cycle interval.
However, these references do not appear to anticipate or explicitly teach the subject matter determined to be allowable.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN B ROCHE whose telephone number is (571)270-1721. The examiner can normally be reached Monday-Friday, 10:30 - 7.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.B.R/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Prosecution Insights