Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant’s arguments, filed April 13th, 2026, with respect to the claim objections and specification objection have been fully considered and are persuasive. The objections have been withdrawn.
2. Applicant's arguments filed April 13th, 2026 have been fully considered but they are not persuasive.
As Applicant’s arguments are directed toward aspects of the claims modified or added via amendment, they will be addressed in the rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-5, 7-9, and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bondarenko et al (US 2022/0244919, herein Bondarenko) in view of Shekhara et al (US 2024/0176663, herein Shekhara).
Regarding claim 1, Bondarenko teaches a processor comprising a neural processing unit ([0003], [0054], NPU), wherein the neural processing unit comprises:
a handling unit ([0054], DMA engine 36) configured to:
obtain a description of a task that involves data in a multi-dimensional tensor in a storage, wherein the tensor comprises a first segment and a second segment ([0053], processing task, [0071], instructions & [0008-0010], [0066], multidimensional tensors stored in memory & [0034], [0077], claim 9, tensors organized into blocks and sub-blocks to be read in sequence), and
control a storage access controller ([0054], memory access controller 37) to load multi-dimensional bricks from the tensor, wherein the multidimensional bricks comprise a brick of the data read from the first segment of the tensor ([0069], load tensor from memory by DMA engine, [0034], [0077], claim 9, tensors organized into blocks and sub-blocks to be read in sequence);
the storage access controller configured to:
identify a location of the brick of the data in the storage using a stride of the data in a dimension of the tensor ([0099-0102], define stride of each dimension to access tensor according to format),
load the brick of the data from the location of the brick of the data in the storage ([0069], load tensor),
determine a virtual stride in the dimension of the first segment of the tensor based on the stride of the second segment of the data in the dimension of the tensor ([0099-0102], determine stride according to size and dimension of tensors),
identify a location of another brick of the data in the storage using the determined virtual stride ([0099-0102], using stride to load blocks of tensor data), and
load the brick of the data from the location of the brick of the data in the storage ([0069], load tensor).
Bondarenko fails to teach wherein the handling unit is to issue invocation data, the storage access controller configured to receive the invocation data from the handling unit, or wherein the tensor data is primary data and auxiliary data read from the first and second segment of the tensor.
Shekhara teaches a processor comprising a neural processing unit ([0264], PPU implements neural network) and a handling unit configured to issue invocation data ([0271-0272], scheduler unit tracks and issues tasks), a storage access controller configured to receive the invocation data from the handling unit ([0079], [0171], [0174], tensor memory access unit) and wherein tensor data is primary data and auxiliary data read from a first and second segment of the tensor ([0079-0080], [0094], [0230-0232], first and second tile or subtensor of tensor data, first and second tensors may be stored in multiple memories).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Bondarenko and Shekhara to utilize a unit for issuing data requests and handle tensors as primary and auxiliary subgroups. While Bondarenko does disclose that a direct memory access engine handles memory requests for tensor data, and that tensors consist of multiple sub-blocks, Bondarenko does not explicitly disclose the use of conventional front-end hardware units such as an issue or scheduling unit. Additionally, while Bondarenko does disclose tensors being addressed and loaded in multiple sub-blocks, these are not explicitly classified as primary and auxiliar sets of data. However, as both references disclose memory management techniques for operating on tensor data that is split into smaller sections, and front-end scheduling hardware is a routine and conventional aspect of the microprocessor art, this combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Bondarenko and Shekhara teaches the processor according to claim 1, wherein at least one of: (i) the neural processing unit is configured to identify the location of the brick of the primary data by multiplying a coordinate of the brick of primary data in the dimension of the tensor by the stride in the dimension (Bondarenko [0099-0102], multiplying stride dimensions to locate tensor data);
(ii) the neural processing unit is configured to identify a location of a brick of auxiliary data by multiplying a coordinate of the brick of the auxiliary data in the dimension of the tensor by the virtual stride in the dimension (Bondarenko [0099-0102], multiplying stride dimensions to locate tensor data); and
(iii) for the dimension of the tensor, the stride is one (Shekhara [0216], traversalStride equaling one).
Regarding claim 5, the combination of Bondarenko and Shekhara teaches the processor according to claim 1, wherein determining the virtual stride from the stride of the primary data comprises multiplying or dividing the stride by a multiple of two (Shekhara [0214], travesalStride equaling two & Bondarenko [0099-0102], multiplication of stride values).
Regarding claim 7, the combination of Bondarenko and Shekhara teaches the processor according to claim 1, wherein the primary data comprises tensor element values (Bondarenko [0062], [0099], tensor data includes elements with numerical values).
Regarding claim 8, the combination of Bondarenko and Shekhara teaches the processor according to claim 7, wherein the auxiliary data comprises scale values, wherein the processor is configured to multiply the tensor element values by the scale values (Shekhara [0167], normalization layer or kernel applies a scale value to each tensor element).
Regarding claim 9, the combination of Bondarenko and Shekhara teaches the processor according to claim 8, wherein one scale value is provided per predetermined number of tensor element values (Shekhara [0167], kernel checks each element to apply scale value).
Regarding claim 12, the combination of Bondarenko and Shekhara teaches the processor according to claim 1, wherein the processor is configured to combine the primary data and auxiliary data to obtain decompressed tensor element values (Bondarenko [0057], [0104-0107], decompression of tensor element values & Shekhara [0079-0080], [0094], [0230-0232], first and second tile or subtensor of tensor data).
Regarding claim 13, the combination of Bondarenko and Shekhara teaches the processor according to claim 1, wherein the processor is configured to access the primary data and the auxiliary data from the first segment and the second segment of the tensor respectively, wherein each of the first segment and the second segment has a separate start address within the tensor (Shekhara [0079-0080], [0085], tensor map addressing, [0094], [0230-0232], first and second tile or subtensor of tensor data).
Regarding claim 14, the combination of Bondarenko and Shekhara teaches the processor according to claim 1, wherein the brick of primary data has a different size in one or more dimensions of the tensor than the brick of auxiliary data (Bondarenko [0068], [0070], [0100], different tensor dimension sizes & Shekhara [0079-0080], [0094], [0230-0232], first and second tile or subtensor of tensor data).
Regarding claim 15, the combination of Bondarenko and Shekhara teaches the processor according to claim 1, wherein each stride is a multiple of a unit size, the unit size depends on the format of data stored in the tensor, and the unit size is specified in a description of the tensor stored in the storage (Bondarenko [0099-0102], strides calculated based on dimension unit size & Shekhara [0068], tensor descriptors).
Regarding claim 16, the combination of Bondarenko and Shekhara teaches the processor according to claim 1, wherein the one or more stride of the primary data is stored in a description of the tensor stored in the storage (Shekhara [0068], [0080], tensor descriptors, global and element stride values).
Regarding claim 17, the combination of Bondarenko and Shekhara teaches the processor according to claim 1, wherein at least one of:
(i) the brick of primary data has four or more dimensions and a size of the brick of the primary data in at least one dimension of the tensor is one (Shekhara [0216], traversalStride equaling one, Bondarenko [0060-0062], four dimensional tensors); and
(ii) the brick of auxiliary data has four or more dimensions and a size of the brick of the auxiliary data in at least one dimension of the tensor is one (Shekhara [0216], traversalStride equaling one, Bondarenko [0060-0062], four dimensional tensors).
Claim 18 refers to a system embodiment comprising the processor of claim 1, further comprising:
the processor implemented in at least one packaged chip (Shekhara [0090], system-on-chip);
at least one system component (Bondarenko Fig 3, [0054], system 31 & components); and
a board, wherein the at least one packaged chip and the at least one system component are assembled on the board (Shekhara [0307], components included on motherboard chipset).
Claim 19 refers to a chip-containing product comprising the system of claim 18, wherein the system is assembled on a further board with at least one other product component (Shekhara [0072], [0307], system on motherboard including multiple processors and GPUs).
Claim 20 refers to a method embodiment of the processor embodiment of claim 1. Therefore, the above rejection for claim 1 is applicable to claim 20.
Allowable Subject Matter
4. Claims 21-22 are allowed.
5. Claims 6, 10, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
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