DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 2 – 6, 14 – 16, and 20 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Han et al. (US publication Number 2009/0103374, hereinafter “Han”) in view of Kodama (US Publication Number 2008/0148010).
4. As per claim 2, Han teaches a memory module comprising; a first plurality of memory devices (1711…1713, figure 17) configured as a first rank of memory (Rank0 1710, figure 17); a second plurality of memory devices (1721…1723, figure 17) configured as a second rank of memory (Rank1 1720, figure 17), a plurality of data buffers coupled to the first and second plurality of memory devices, (plurality of associated switching buffers, figure 21, paragraph 214) each data buffer including switching logic (switching logic for each data buffer, paragraphs 210 and 211) to route data, selected (selection from rank 1854, figure 19) from the first rank of memory and the second rank of memory to external data lines (memory to external data lines, figure 19, paragraphs 212 – 214); and a command buffer to receive commands from an external memory controller, the command buffer to control routing of the data in the plurality of data buffers (command address handling for rank, figures 19 and 21, with memory buffer utilized in the routing, paragraphs 215 – 217 along path CA to 2102/2110).
Han does not appear to explicitly disclose routing of the data by a switching logic in the plurality of data buffers.
However, Kodama discloses routing of the data by a switching logic in the plurality of data buffers (paragraphs 50 and 52, switch 104, coupled to the memory and data transfer unit 108 to handle data buffer functionality, figure 1 with the internals of 108 further seen in figure 4 which also displays the plurality of buffers 406/407).
Han and Kodama are analogous art because they are from the same field of endeavor of memory handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Han and Kodama before him or her, to modify the routing of Han to include the routing pathways of Kodama because it would allow for flexibility in data buffer transactions.
One of ordinary skill would be motivated to make such modification in order to enhance data path flexibility in a memory system (paragraph 3). Therefore, it would have been obvious to combine Kodama with Han to obtain the invention as specified in the instant claims.
5. As per claims 14 and 20, Han teaches a module and method for operating a memory module comprising: receiving a command at command buffer (command address handling for rank, figures 19 and 21, with memory buffer utilized in the routing, paragraphs 215 – 217 along path CA to 2102/2110) from an external memory controller (memory controller 1870, figure 19); selecting (selection from rank 1854, figure 19), based on the command, a switching configuration (switching logic for each data buffer, paragraphs 210 and 211) of a plurality of data buffers to couple external data lines to either a first plurality of memory devices of the memory module configured as a first rank of memory (Rank0 1710, figure 17) or a second plurality of memory devices of the memory module configured as a second rank (Rank1 1720, figure 17); receiving data at the plurality of data buffers from external data lines (plurality of associated switching buffers, figure 21, paragraph 214); and routing, by the plurality of data buffers, the data to either the first plurality of memory devices configured as the first rank of memory or the second plurality of memory devices configured as the second rank based on the switching configuration (routing according to the rank, paragraphs 218- 221).
Han does not appear to explicitly disclose routing of the data by a switching logic in the plurality of data buffers.
However, Kodama discloses routing of the data by a switching logic in the plurality of data buffers (paragraphs 50 and 52, switch 104, coupled to the memory and data transfer unit 108 to handle data buffer functionality, figure 1 with the internals of 108 further seen in figure 4 which also displays the plurality of buffers 406/407).
Han and Kodama are analogous art because they are from the same field of endeavor of memory handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Han and Kodama before him or her, to modify the routing of Han to include the routing pathways of Kodama because it would allow for flexibility in data buffer transactions.
One of ordinary skill would be motivated to make such modification in order to enhance data path flexibility in a memory system (paragraph 3). Therefore, it would have been obvious to combine Kodama with Han to obtain the invention as specified in the instant claims.
6. Han modified by the teachings of Kodama as seen in claim 1 above, as per claim 3, Han teaches a module, wherein the command buffer is configured to receive a chip select signal associated with a command and to control the routing for of the data based on the chip select signal plurality of associated switching buffers, figure 21, paragraph 214).
7. Han modified by the teachings of Kodama as seen in claim 1 above, as per claims 4 and 16, Kodama teaches a module and method, wherein the switching logic comprises a full crossbar switch (104, figure 1).
8. Han modified by the teachings of Kodama as seen in claim 1 above, as per claim 5, Han teaches a module, wherein the plurality of data buffers comprises a plurality of distributed microbuffer chips (2142/2160/2162, figure 21).
9. Han modified by the teachings of Kodama as seen in claim 1 above, as per claim 6, Han teaches a module, wherein the plurality of data buffers are integrated in a central buffer chip (2116, figure 21).
10. Han modified by the teachings of Kodama as seen in claim 14 above, as per claim 15, Han teaches a method, wherein routing the data is based on a chip select signal associated with the command (C/A 1854, figure 19), .
Allowable Subject Matter
11. Claims 7 – 13, 17 – 19, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
12. Applicant’s arguments with respect to claims 2 – 21 have been considered but are moot because the new ground of rejection in light of Kodama does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chowdhuri/Kucharewski/Xiong has teachings of switching logic handling routing for data buffers.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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