/DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final communication in response to communication filed 10/17/24.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
With respect to claim 13, the recitation “a target reference voltage and a first rail voltage” is indefinite because it’s unclear if the targe reference and first rail voltage are the same as or in addition to the respective reference voltage and plurality of power rails of claim 1.
Claims 14 and 15 contain the same issues of claim 13.
With respect to claims 13 and 17, the recitation “a first voltage regulator cell” is indefinite because it’s unclear if it’s part of or in addition to the array of voltage regulator cells.
With respect to claim 16, the recitation “each voltage regulator cell” is indefinite because it’s unclear if it’s part of or in addition to the array of voltage regulator cells.
With respect to claim 17, the recitation “a target reference voltage” and “a first rail voltage” is indefinite because it’s unclear if the targe reference and first rail voltage are the same as or in addition to the respective reference voltage and plurality of power rails of claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,3-13, 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zou et al. 20220247315.
With respect to claim 1, figures 4A, 4B, 5, 6, and 9 disclose an electronic system, comprising:
an array of voltage regulator cells [402s, figs 4A,4B,6 and detail Fig. 9], wherein the array of voltage regulator cells is configured to provide a plurality of voltage regulator sets [figs. 4A,4B and 6, set of 402s connected to each 206-1/2/3/4], and each voltage regulator set is configured to output a respective rail voltage [Fig. 6, VR1/2/3/4] and provide the respective rail voltage to a respective power rail of a plurality of power rails [206-1/2/3/4]; and
a plurality of reference circuits [fig. 6, 602, 612, 610; fig. 9, DACs for VRs connected to each power rail 206] coupled to the array of voltage regulator cells [fig. 9 detail of 402], wherein each of the plurality of reference circuits is shared by, and configured to provide a respective reference voltage [906 output of DACs controlled by 610 for each set of VRs] to, one or more respective voltage regulator cells of a respective voltage regulator set, and the respective voltage regulator set is configured to generate the respective rail voltage based on the respective reference voltage. [para 0116]
With respect to claim 3, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 1, wherein the plurality of power rails include a first number of power rails [4] , and the plurality of reference circuits include a second number of reference circuits [4, part of 602 generating 610 for set of DACs associated with each subset of 402s], the second number equal to or less than the first number. [0095, Power array controller 602 is configured to determine a control value 610 based on at least the respective rail voltage V.sub.R, and to provide the determined control value 610 to the subset of voltage regulators 402 corresponding to the respective power rail 206]
With respect to claim 4, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 1, wherein each of the plurality of power rails [206- 1/2/3/4] is uniquely associated with a distinct one of the plurality of reference circuits [parts of 602 generate 4 610s for 4 sets of DACs in each set of 402s], which is configured to provide the respective reference voltage to each voltage regulator cell in the respective voltage regulator set. [0095, DACs of each subset of 402s receive same control value 610]
With respect to claim 5, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 1, wherein: the plurality of power rails include a first number of power rails [4]; the plurality of reference circuits include a second number of reference circuits [4]; the array of voltage regulator cells includes a third number of voltage regulator cells [60]; the second number is equal to or less than (≤) the third number; and the first number is equal to or less than (≤) the third number.
With respect to claim 6, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 1, wherein the plurality of voltage regulator sets include a first voltage regulator set [DACs of 402s associated with 206-1] that is configured to output a first rail voltage [VR1] to a first power rail [206-1], and the first rail voltage is equal to a first reference voltage [906 for DACs of VR 402s] provided by a first reference circuit [DACs of 402s providing 206-1]. [para 0116]
With respect to claim 7, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 6, further comprising a voltage controller coupled to the plurality of reference circuits, wherein the voltage controller [602 provides 610] is configured to generate a digital control signal [610] based on the first rail voltage associated with the first power rail and provide the digital control signal to the first reference circuit defining the first reference voltage. [0095]
With respect to claim 8, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 6, wherein: the first voltage regulator set [402s of 206-1] further includes a target number of voltage regulator cells and is configured to deliver up to a predefined regulator current [IR1] to the first power rail; and the target number is determined based on the predefined regulator current. [The number of regulators in the set determines the current output.]
With respect to claim 9, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 8, further comprising a voltage controller [602] coupled to [610] the array of voltage regulator cells [DACs of each set of VRs];
wherein the voltage controller is configured to determine the target number based on the predefined regulator current associated with the first power rail, generate one or more select signals [enable 612] based on the target number, and provide the one or more select signals to the array of voltage regulator cells to select the target number of voltage regulator cells of the first voltage regulator.
With respect to claim 10 figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 1, wherein voltage regulator cells in the array of voltage regulator cells are identical to each other. [para 0082, can be identical]
With respect to claim 11, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 1, wherein at least two voltage regulator cells in the array of voltage regulator cells are different from one another. [para 0082 can be differently configured]
With respect to claim 12, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 1, wherein the plurality of reference circuits are identical to one another. [all DACs]
With respect to claim 13, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 1, wherein a first voltage regulator cell further comprises:
a first signal generator [904 812] configured to receive a target reference voltage [906] and a first rail voltage [206] and generate a periodic signal [816] having a target pulse width; and
a first power stage [810,820] coupled to the first signal generator and configured to generate the first rail voltage based on the periodic signal having the target pulse width; and
a first feedback path [822] coupling an output of the first power stage to a signal input of the first signal generator.
With respect to claim 16, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 1, wherein each voltage regulator cell further comprises:
an error amplifier[612] configured to receive the respective reference voltage and the respective rail voltage and generate an amplified difference signal [808];
a pulse width modulator [812] coupled to the error amplifier and configured to generate a periodic signal [816] having a pulse width and a feature frequency;
a power stage [810] coupled to the pulse width modulator and configured to generate the respective rail voltage based on the periodic signal; and
a feedback path [822] coupling an output of the power stage to an input of the error amplifier.
With respect to claim 17, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 1, wherein a first voltage regulator cell further comprises:
an input reference interface [receives 906] for receiving a target reference voltage;
an input signal interface [receives 822] for receiving an input signal;
an output interface [output of 810] for providing a first rail voltage to a first rail;
a first feedback path [822] coupling the output interface of the first voltage regulator cell to the input signal interface of the first voltage regulator cell; and
an inductor [820] electrically coupled between the input signal interface and the output interface.
With respect to claim 18, figures 4A, 4B, 5, 6, and 9 disclose the electronic system of claim 17, wherein the inductor includes one of an integrated inductor formed on a substrate of an integrated circuit including a subset of the array of voltage regulator cells or a hybrid inductor assembled onto the substrate.
With respect to claim 19, figures 4A, 4B, 5, 6, and 9 disclose an apparatus, comprising:
a plurality of power rails [206-1/2/3/4] configured to providing one or more rail voltages; an array of voltage regulator cells [402] coupled to the plurality of power rails, wherein the array of voltage regulator cells is configured to provide a plurality of voltage regulator sets [groups of 402’s providing 206’s], and each voltage regulator set is configured to output a respective rail voltage to a respective power rail; and
a plurality of reference circuits [fig. 9 DACs] coupled to the array of voltage regulator cells, wherein each of the plurality of reference circuits is shared by, and configured to provide a respective reference voltage [906] to, one or more respective voltage regulator cells of a respective voltage regulator set, and the respective voltage regulator set is configured to generate the respective rail voltage based on the respective reference voltage. [para 0116]
With respect to claim 20, figures 4A, 4B, 5, 6, and 9 disclose a method, comprising:
grouping voltage regulator cells [402] in an array of voltage regulator cells to provide a plurality of voltage regulator sets [groups of 402 providing 206]; and
for each of the plurality of voltage regulator sets:
generating a respective reference voltage [906] by a respective one of a plurality of reference circuits [902], wherein the respective one of the plurality of reference circuits is shared by one or more respective voltage regulator cells of the respective voltage regulator set;
generating a respective rail voltage [VR] by the respective voltage regulator set based on the respective reference voltage; and providing the respective rail voltage to drive a respective one of a plurality of power rails [206]. [para 0116]
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Zou et al. 20220247314.
With respect to claim 2, figures 4A, 4B, 5, 6, and 9 disclose the electronic system for claim 1, further comprising a substrate, but does not disclose wherein the array of voltage regulator cells and the plurality of reference circuits are disposed on the substrate, separately from one another.
However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the voltage regulator cells and reference circuit disposed on the substrate separately from one another since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached 8:30 - 5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Ryan Jager/Primary Examiner, Art Unit 2842 3/5/26
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