DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim status
Claims 1-20 are pending; claims 1, 18 and 20 are independent.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 2024/0282246), and further in view of Heo (US 2023/0010792).
Regarding claim 1, Jang teaches a driver (fig. 5) including a plurality of stages (Para 0101 and a plurality of stages GS1, GS2, GS3, . . . , GS(N-2), GS(N-1), and GS(N)), at least one stage of the plurality of stages comprising:
an input circuit configured to transfer an input signal to a first node in response to a clock signal (fig.7, input circuit ISC includes transistor TS1 receives start signal VST in response to clock signal CLK1 and provides signal VST to the Q node, transistor TS2 receives reverse start signal VST_R in response to clock signal CLK1_R and provides signal VST_R to the Q node; Paras 0156-0157);
a first transistor connected between the first node and a second node (fig. 7 and Para 0133, wherein transistor TB1 connected between Q node and node QA);
a carry circuit (fig. 7, TH2, T12) configured to output a carry signal having a first high gate voltage when the second node has the first high gate voltage (fig.7, Para 0131, gate of transistor T12 is connected to the Q node and provides a low voltage VGL to the carry node), and to output a first high gate voltage to the carry output node in response to a voltage of the inverting control node (fig.7, Para.0127, gate of transistor TH2 is connected to QB node and provides high voltage VGH to the carry node); and
a level shifting output circuit configured to output an output signal having a second high gate voltage (fig. 7, Paras 0110 and 0126, wherein the gate of the first transistor TH1 connected to the QB node and provides a high voltage VGH to the output node EM).
Jang does not expressly discloses a second high gate voltage higher than the first high gate voltage by level-shifting the first high gate voltage of the second node.
However, Heo discloses a second high gate voltage higher than the first high gate voltage by level-shifting the first high gate voltage of the second node, see fig.5, para.0071-0072; gate transistor TR2 connected to control node QB/Q(Qb), a first electrode of TR2 is connected to a second power node that may receive a high voltage GVDD2 different from a first high gate voltage GVDD1, and second electrode of TR2 connected to output EMOUT(n); fig.4a-b para.0061-0067).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a driver of Jang with the teaching of Heo, such that a second high voltage (as disclosed by Heo) is provided to the output node EM in response to the Qb node (of Jang) and second low voltage (as disclosed by Heo) is provided to the output node EM in response to the Q node (of Jang). The motivation being to alternately control the first and second control nodes to act as pull-up control node and a pull-down control node and may be alternatively activated to achieve a narrow bezel of a display device and reduce stress on buffer transistors of a gate driving circuit (Para 0176, Heo).
Regarding claim 2, Jang in view of Heo teaches the driver of claim 1, wherein the clock signal toggles between a low gate voltage and the first high gate voltage (Para 0164, Jang).
Regarding claim 3, Jang in view of Heo teaches the driver of claim 1, wherein the level shifting output circuit includes at least one p type metal-oxide-semiconductor (PMOS) transistor (fig. 7, TH1, Paras 0110 and 0126, wherein the gate of the first transistor TH1 connected to the QB node and provides a high voltage VGH to the output node EM and Para 0122, is configured as a P-type transistor, Jang) and
wherein a first active region of the PMOS transistor includes a material different from a material of a second active region of the NMOS transistor (Para 0092,Jang).
Jang in view of Heo does not expressly discloses the level shifting output circuit includes at least one n-type metal-oxide-semiconductor (NMOS) transistor.
However, Jang discloses an example where the transistors configured as P-type transistor, which suggests that the transistors may be configured as N-type transistor (Jang, Para 0122). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Jang in view of Heo, by implementing at least one transistor (fig. 7, TI1) as N-type transistor, since in doing so would not have modified the operation of the device, and yielding predictable results.
Regarding claim 4, Jang in view of Heo teaches the driver of claim 3, wherein the level shifting output circuit further includes at least one capacitor connected between a gate of the PMOS transistor and a gate of the NMOS transistor (fig. 5, C3 and Para 0073, wherein one electrode of capacitor C3 connected to the gate of TR1 (NMOS transistor) and the second electrode is connected to the gate of TR2 via a capacitor C4, Heo).
Claim 4 has limitations (PMOS and NMOS transistor) similar to those of Claim 3 and are met by the references as set forth above.
Regarding claim 5, Jang in view of Heo teaches the driver of claim 1, wherein the first transistor (fig. 7, TB1) includes a gate receiving a low gate voltage to VGL, a first terminal connected to the first node, and a second terminal connected to the second node (fig. 7, TB. And Para 0133, wherein a gate electrode of the first buffer transistor TB1 is connected to the low voltage line, a first source/drain electrode thereof is connected to the QA node, and a second source/drain electrode thereof is connected to the Q node, Jang)
Regarding claim 6, Jang in view of Heo teaches the driver of claim 1, wherein the input circuit includes: a second transistor (fig.7, TS1) including a gate receiving the clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node (fig.7 and Para 0156, wherein input circuit ISC includes transistor TS1 receives start signal VST in response to clock signal CLK1 and provides signal VST to the Q node, Jang).
Regarding claim 7, Jang in view of Heo teaches the driver of claim 6, wherein the input circuit further includes: a third transistor (fig. 7, TS2) including a gate receiving an inverted clock signal, a first terminal receiving the input signal, and a second terminal connected to the first node (fig. 7, TS2 and para 0157, wherein a gate electrode of the second transistor TS2 is connected to the first reverse clock signal line, a first source/drain electrode thereof is connected to the reverse start signal line, and a second source/drain electrode thereof is connected to the Q node, Jang), wherein the second transistor is a PMOS transistor (fig. 7 and Para 0122, Jang), and
Jang in view of Heo does not expressly discloses wherein the third transistor is an NMOS transistor.
However, Jang discloses an example where the transistors configured as P-type transistor, which suggests that the transistors may be configured as N-type transistor (Jang, Para 0122). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Jang in view of Heo, by implementing the third transistor (fig. 7, TS2) as N-type transistor, since in doing so would not have modified the operation of the device, and yielding predictable results.
Regarding claim 8, Jang in view of Heo teaches the driver of claim 1, wherein the carry circuit (fig. 7, TH2 and T12) includes: a fourth transistor (fig. TH2) including a gate connected to a third node, a first terminal receiving the first high gate voltage, and a second terminal connected to a carry node at which the carry signal is output (fig.7, Para.0127, a gate of transistor TH2 is connected to QB node and provides high voltage VGH to the carry node, Jang); and
a fifth transistor (fig. 7, T12) including a gate connected to the second node, a first terminal connected to the carry node, and a second terminal receiving a low gate voltage (fig.7, Para 0131, a gate of transistor T12 is connected to the QA node and provides a low voltage VGL to the carry node, Jang).
Regarding claim 9, Jang in view of Heo teaches the driver of claim 8, wherein the carry circuit further includes: a first capacitor including a first electrode connected to the carry node, and a second electrode connected to the second node (fig. 7, C1, wherein a first electrode connected to the carry node (CO) via TR2 and TH2 and a second electrode connected to QA node, Jang).
Regarding claim 20, Jang teaches a display device (fig. 1, a display device 100) comprising:
a display panel including a plurality of pixels (fig. 1, the display panel PN and Para 0052);
a data driver configured to provide data signals to the plurality of pixels (fig. 1, a data driver DD and Para 0056);
a gate driver configured to provide gate signals to the plurality of pixels (fig. 1, a gate driver GD and Para 0055);
an emission driver configured to provide emission signals to the plurality of pixels (fig. 1, a gate driver GD and Paras 0066-0067);and
a controller configured to control the data driver, the gate driver, and the emission driver (fig. 1, a timing controller TC and Para 0057),
wherein at least one of the gate driver and the emission driver includes a plurality of stages (Para 0101 and a plurality of stages GS1, GS2, GS3, . . . , GS(N-2), GS(N-1), and GS(N)), and wherein at least one stage of the plurality of stages comprises:
an input circuit configured to transfer an input signal to a first node in response to a clock signal (fig.7, input circuit ISC includes transistor TS1 receives start signal VST in response to clock signal CLK1 and provides signal VST to the Q node, transistor TS2 receives reverse start signal VST_R in response to clock signal CLK1_R and provides signal VST_R to the Q node; Paras 0156-0157);
a first transistor connected between the first node and a second node (fig. 7 and Para 0133, wherein transistor TB1 connected between Q node and node QA);
a carry circuit (fig. 7, TH2, T12) configured to output a carry signal having a first high gate voltage when the second node has the first high gate voltage (fig.7, Para 0131, gate of transistor T12 is connected to the Q node and provides a low voltage VGL to the carry node), and to output a first high gate voltage to the carry output node in response to a voltage of the inverting control node (fig.7, Para.0127, gate of transistor TH2 is connected to QB node and provides high voltage VGH to the carry node); and
a level shifting output circuit configured to output an output signal having a second high gate voltage (fig. 7, Paras 0110 and 0126, wherein the gate of the first transistor TH1 connected to the QB node and provides a high voltage VGH to the output node EM).
Jang does not expressly discloses a second high gate voltage higher than the first high gate voltage by level-shifting the first high gate voltage of the second node.
However, Heo discloses a second high gate voltage higher than the first high gate voltage by level-shifting the first high gate voltage of the second node, see fig.5, para.0071-0072; gate transistor TR2 connected to control node QB/Q(Qb), a first electrode of TR2 is connected to a second power node that may receive a high voltage GVDD2 different from a first high gate voltage GVDD1, and second electrode of TR2 connected to output EMOUT(n); fig.4a-b para.0061-0067).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a driver of Jang with the teaching of Heo, such that a second high voltage (as disclosed by Heo) is provided to the output node EM in response to the Qb node (of Jang) and second low voltage (as disclosed by Heo) is provided to the output node EM in response to the Q node (of Jang). The motivation being to alternately control the first and second control nodes to act as pull-up control node and a pull-down control node and may be alternatively activated to achieve a narrow bezel of a display device and reduce stress on buffer transistors of a gate driving circuit (Para 0176, Heo).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 2024/0282246), in view of Heo (US 2023/0010792), and further in view of Kwon (US 6,043,679).
Regarding claim 17, Jang in view of Heo teaches the driver of claim 1, wherein a second low gate voltage of the output signal is lower than a first low gate voltage of the input signal, the clock signal, and the carry signal (fig.5 and Paras 0071- 0072, gate of transistor TR1 is connected to control node Q/QB (Qn), a first electrode of TR1 is connected to a first power node that may receive a low gate voltage GVSS0 different from a first low gate voltage GVSS, GVSS2, and second electrode of TR1 is connected to output node EMOUT(n); fig.4a-b, Paras 0061-0067, Heo),
Jang in view of Heo does not expressly disclose wherein the at least one stage further includes: a second transistor connected in series with the first transistor between the first node and the second node, wherein the first and second transistors are different types of transistors.
However, Kwon discloses wherein the at least one stage further includes: a second transistor connected in series with the first transistor between the first node and the second node, wherein the first and second transistors are different types of transistors, see fig. 5A, col. 4 and lines 9-21.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a driver of Jang in view of Heo with the teaching of Kwon, including a PMOS and NMOS transistors P3 and N3 coupled in series between the applied voltages of 10 V and -10 V, as a known technique to yield a predictable result.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang (US 2024/0282246), in view of Heo (US 2023/0010792), and further in view of Kogure (US 2001/0017608).
Regarding claim 18, Jang teaches a driver (fig. 5) including a plurality of stages (Para 0101 and a plurality of stages GS1, GS2, GS3, . . . , GS(N-2), GS(N-1), and GS(N)), at least one stage of the plurality of stages comprising:
an input circuit configured to transfer an input signal to a first node in response to a clock signal (fig.7, input circuit ISC includes transistor TS1 receives start signal VST in response to clock signal CLK1 and provides signal VST to the Q node, transistor TS2 receives reverse start signal VST_R in response to clock signal CLK1_R and provides signal VST_R to the Q node; Paras 0156-0157);
a first transistor connected between the first node and a second node (fig. 7 and Para 0133, wherein transistor TB1 connected between Q node and node QA);
a carry circuit (fig. 7, TH2, T12) configured to output a carry signal having a first high gate voltage when the second node has the first high gate voltage (fig.7, Para 0131, gate of transistor T12 is connected to the Q node and provides a low voltage VGL to the carry node), and to output a first high gate voltage to the carry output node in response to a voltage of the inverting control node (fig.7, Para.0127, gate of transistor TH2 is connected to QB node and provides high voltage VGH to the carry node);
a level shifter circuit configured to level-shift the first high gate voltage of the second node such that a third node has a second high gate voltage (fig. 7, Paras 0110 and 0126, wherein the gate of the first transistor TH1 connected to the QB node and provides a high voltage VGH to the output node EM);
Jang does not expressly discloses a second high gate voltage higher than the first high gate voltage by level-shifting the first high gate voltage of the second node.
However, Heo discloses a second high gate voltage higher than the first high gate voltage, see fig.5, para.0071-0072; gate transistor TR2 connected to control node QB/Q(Qb), a first electrode of TR2 is connected to a second power node that may receive a high voltage GVDD2 different from a first high gate voltage GVDD1, and second electrode of TR2 connected to output EMOUT(n); fig.4a-b para.0061-0067).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a driver of Jang with the teaching of Heo, such that a second high voltage (as disclosed by Heo) is provided to the output node EM in response to the Qb node (of Jang) and second low voltage (as disclosed by Heo) is provided to the output node EM in response to the Q node (of Jang). The motivation being to alternately control the first and second control nodes to act as pull-up control node and a pull-down control node and may be alternatively activated to achieve a narrow bezel of a display device and reduce stress on buffer transistors of a gate driving circuit (Para 0176, Heo).
Jang in view of Heo does not expressly discloses a second transistor connected between the third node and a fourth node and configured to transfer the second high gate voltage of the third node to the fourth node; and a level-shifting output circuit configured to output an output signal having a third high gate voltage higher than the second high gate voltage by level-shifting the second high gate voltage of the fourth node.
However, Kogure discloses a second transistor connected between the third node and a fourth node and configured to transfer the second high gate voltage of the third node to the fourth node; and a level-shifting output circuit configured to output an output signal having a third high gate voltage higher than the second high gate voltage by level-shifting the second high gate voltage of the fourth node, see 2A/B, 3A/B and Paras 0065-0071.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a driver of Jang in view of Heo with the teaching of Kogure, including a first level shifter 101, the logic-based high level pulse (standard VDD) is generated to provide GVDD and then shifted to the TFT-based on-level in order to produce GVDD as shown in the center of FIG. 2A and in the second level shifter 102, the logic-based low level pulse (standard VSS) is generated to provide GVSS and then shifted to the TFT-based off-level in order to produce GVSS as shown in the bottom of FIG. 2A. In more detail, in the first level shifter 201, the logic-based low level pulse (standard VSS) is shifted to generate GVSS and then shifted to the TFT-based off-level in order to produce GVSS as shown in the bottom of FIG. 3A. In the second level shifter 202, the logic-based high level pulse (standard VDD) is shifted to generate GVDD and then shifted to the TFT-based on-level in order to produce GVDD as shown in the center of FIG. 3A, as a known technique to yield a predictable result.
Allowable Subject Matter
Claims 10-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As claim 10, the prior art either alone or in obvious combination does NOT teach ALL of the limitations including:
wherein the level shifting output circuit includes:
a sixth transistor including a gate connected to a fourth node, a first terminal receiving the second high gate voltage, and a second terminal connected to a third node;
a seventh transistor including a gate connected to the second node, a first terminal connected to the third node, and a second terminal receiving a low gate voltage;
an eighth transistor including a gate connected to the third node, a first terminal receiving the second high gate voltage, and a second terminal connected to the fourth node;
a ninth transistor including a gate connected to the second node, a first terminal connected to the fourth node, and a second terminal receiving the low gate voltage; and
a second capacitor including a first electrode connected to the fourth node, and a second electrode connected to the second node, as recited in claim 10.
As claim 14, the prior art either alone or in obvious combination does NOT teach ALL of the limitations including:
wherein the level shifting output circuit includes:
a sixth transistor including a gate connected to a fourth node, a first terminal receiving the second high gate voltage, and a second terminal connected to a third node;
a seventh transistor including a gate connected to the second node, a first terminal connected to the third node, and a second terminal receiving a low gate voltage;
an eighth transistor including a gate connected to the third node, a first terminal receiving the second high gate voltage, and a second terminal connected to the fourth node;
a ninth transistor including a gate connected to the third node, a first terminal connected to the fourth node, and a second terminal receiving the low gate voltage; and
a second capacitor including a first electrode connected to the fourth node, and a second electrode connected to the second node, as recited in claim 14.
As claim 19, the prior art either alone or in obvious combination does NOT teach ALL of the limitations including:
wherein the at least one stage further includes: a third transistor connected in series with the first transistor between the first node and the second node; and
a fourth transistor connected in series with the second transistor between the third node and the fourth node,
wherein the first and third transistors are different types of transistors, wherein the second and fourth transistors are different types of transistors,
wherein a second low gate voltage of the third node is lower than a first low gate voltage of the input signal, the clock signal, and the carry signal, and wherein a third low gate voltage of the output signal is lower than the second low gate voltage of the third node. as recited in claim 19.
Claims 10-13 and 15-16 depend on objection claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Han (US 2016/0064098), relates to the field of organic light-emitting display, in particular to a shift register unit, a method for driving the same, a shift register and a display device.
Chung (US 2019/0378462), relate to a scan driver for sequentially driving and simultaneously driving a plurality of scan lines, and a display device having the scan driver.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM BODDIE can be reached at (571) 272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.E.E/Examiner, Art Unit 2625 4/30/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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