DETAILED ACTION
Election/Restrictions
Claims 8-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention. Election was made without traverse in the reply filed on 5/15/2026.
Claims 1-7 remain pending and have been examined. This action is non-final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1, 3, 5 and 7 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1, 7 and 12 of prior U.S. Patent No. 11,468,002. This is a statutory double patenting rejection. (Note: dependent claims 3, 5 and 7 each include all limitations of claim 1. Thus, claim 3, including all limitations of claim 1 is the same invention as claim 7 of the Patent reference. Thus, claim 5, including all limitations of claim 1 is the same invention as claim 12 of the Patent reference. Thus, claim 7, including all limitations of claim 1 is the same invention as claim 1 of the Patent reference.)
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 11,468,002. Although the claims at issue are not identical, they are not patentably distinct from each other because each claim of USPAT No. 11,468,002 anticipates the claims of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stewart, PGPUB No. 2004/0133750 (cited on IDS filed on 3/26/2025), and further in view of Li, PGPUB No. 2018/0267931.
In regards to claim 1, Stewart discloses A computing device ([0041, 0117 and 0143]) comprising: an array of processing elements mutually connected to perform single instruction multiple data (SIMD) operations ([0040-0041, 0116-0117 and 0143]: wherein an array of processing elements mutually connected to implement a SIMD processor and thus perform SIMD operations is disclosed (See Figs. 1-3 and 20)) memory cells connected to each processing element to store data related to the SIMD operations ([0040-0043, 0058-0060 and 0143]: wherein memory or storage elements (memory cells) of memory (element 9) are connected to store data related to the SIMD operations (See Figs. 1-3)) and a local memory connected to each processing element to store data related to the SIMD operations ([0040-0046]: wherein a local memory segment is connected to each processor element to store data related to the SIMD operations (see abstract)) wherein a first local memory of a first processing element is connected to a second local memory of a second processing element that is adjacent the first processing element in the array of processing elements. ([0042-0048 and 0052-0054]: wherein a first local memory of a first processing element (e.g. local memory segment for processor element 5) is connected to a second local memory of a second processing element (e.g. local memory segment for processor element 3), via switching elements, I/O ports and buses, that is adjacent the first processing element in the array of processing elements (see abstract and Figs. 1-3))
Stewart does not explicitly disclose caches connected to processing elements. Stewart does disclose local memory segments connected to each processing element. However, Stewart does not explicitly disclose the local memories being cache.
Li discloses caches connected to processing elements to cache data ([0039-0040 and 0051]: wherein a plurality of caches is connected to processing elements (See Figs. 2-3A))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the local memories of Stewart to be cache memories as taught in Li. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (using cache memory as taught in Li) for another (using generic local memory as taught in Stewart) to obtain predictable results (using cache memories as local memories to cache data) (MPEP 2143, Example B). Furthermore, using cache memory can be used for the benefits of reduced processing latency and improving system speed, as it stores frequently accessed data and eliminates the need for a processor to repeatedly access slower main memory.
In regards to claim 2, the combination of Stewart and Li discloses The computing device of claim 1 (see rejection of claim 1 above) wherein the first cache of the first processing element is connected to a third cache of a third processing element that is adjacent the first processing element in the array of processing elements (Stewart [0042-0048 and 0052-0054]: wherein the first local memory of a first processing element (e.g. local memory segment for processor element 5) is connected to a third local memory of a third processing element (e.g. local memory segment for processor element 7), via switching elements, I/O ports and buses, that is adjacent the first processing element in the array of processing elements (see abstract and Figs. 1-3) (Note: Li discloses the caches associated with PEs (See Li: Figs. 2-3A). Thus, the combination of references discloses the above limitations)) wherein the first processing element is positioned between the second and third processing elements in the array of processing elements. (Stewart: See Figs. 1-2: wherein processor element (5) is between the second and third processor elements (3 and 7))
In regards to claim 3, the combination of Stewart and Li discloses The computing device of claim 1 (see rejection of claim 1 above) further comprising a write multiplexer including an output connected to the first cache, wherein selectable inputs of the write multiplexer are connected to a register of the first processing element and to the second cache. (Stewart [0105-0109]: wherein a 2 to 1 output selector switch (element 342) includes an output to a first local memory, wherein selectable inputs to element 342 are connected to a register output of a first PE and a second local memory from line 329 (via selector switch (element 327) and I/O ports) (See Figs. 9-10 and 16-17) (Note: Li discloses the caches associated with PEs (See Li: Figs. 2-3A). Thus, the combination of references discloses the above limitations))
In regards to claim 4, the combination of Stewart and Li thus far discloses The computing device of claim 3 (see rejection of claim 3 above) the computing device further comprises control signals to control the write multiplexer to write to the first cache results and/or input values of operation. (Stewart [0094-0096 and 0105-0109]: wherein a 2 to 1 output selector switch (element 342) writes a register result output from PE ALU based on control signals (See Figs. 9-10 and 16-17) (Note: Li discloses the caches associated with PEs (See Li: Figs. 2-3A). Thus, the combination of references discloses the above limitations))
The combination of Stewart and Li thus far does not explicitly disclose
wherein: the array of processing elements is configured to perform a multiplying accumulation, the computing device further comprises a controller to control the write multiplexer, accumulated results and/or input values of the multiplying accumulation. The embodiments of Stewart in Figs. 1, 9-10 and 16-17 disclose switching elements including selector switches that are controlled by control signals but do not explicitly disclose a controller that outputs control signals.
However, Stewart discloses in the embodiment of Fig. 21 an array controller that applies control signals to control selector switches ([0131]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the control signals of the embodiments of Figs. 1, 9-10 and 16-17 to be applied by a controller as the embodiment of Fig. 21. It would have been obvious to one of ordinary skill in the art because it would have been applying a known technique (using a controller to apply control signals) to a known device (switching element controlled by control signals) ready for improvement to yield predictable results (using a controller to apply control signals to control a switching element) for the benefit of using hardware to apply control signals to efficiently control switching elements (MPEP 2143, Example D).
The combination of Stewart and Li thus far does not disclose
wherein: the array of processing elements is configured to perform a multiplying accumulation nor accumulated results and/or input values of the multiplying accumulation.
Li discloses wherein: the array of processing elements is configured to perform a multiplying accumulation ([0089]) accumulated results and/or input values of the multiplying accumulation. ([0089 and 0103])
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the array of processing elements of Stewart to be able to perform multiply accumulate operations to generate accumulated results as the array of processor elements of Li. It would have been obvious to one of ordinary skill in the art because it would provide added flexibility and increased efficiency by allowing the array of processors to perform additional arithmetic operations (e.g. multiply accumulate operations).
In regards to claim 5, the combination of Stewart and Li discloses The computing device of claim 1 (see rejection of claim 1 above) further comprising a read multiplexer including an output connected to a register of the first processing element, wherein selectable inputs of the read multiplexer are connected to the first cache and to the second cache. (Stewart [0105-0109]: wherein a 2 to 1 output selector switch (element 341) includes an output connected to a register input of a first processing element, wherein selectable inputs to element 341 are connected to a local memory of the first processor element and a second local memory (via selector switch (element 327) and I/O ports) (See Figs. 9-10 and 16-17) (Note: Li discloses the caches associated with PEs (See Li: Figs. 2-3A). Thus, the combination of references discloses the above limitations))
In regards to claim 6, the combination of Stewart and Li thus far discloses The computing device of claim 5 (see rejection of claim 5 above) the computing device further comprises control signals to control the read multiplexer to read from the first cache coefficients and/or input values of the operation. (Stewart [0094-0096 and 0105-0109]: wherein a 2 to 1 output selector switch (element 341) reads input values of ALU operations (See Figs. 9-10 and 16-17) (Note: Li discloses the caches associated with PEs (See Li: Figs. 2-3A). Thus, the combination of references discloses the above limitations))
The combination of Stewart and Li thus far does not explicitly disclose
wherein: the array of processing elements is configured to perform a multiplying accumulation, the computing device further comprises a controller to control the read multiplexer, first cache coefficients and/or input values of the multiplying accumulation. The embodiments of Stewart in Figs. 1, 9-10 and 16-17 disclose switching elements including selector switches that are controlled by control signals but do not explicitly disclose a controller that outputs control signals.
However, Stewart discloses in the embodiment of Fig. 21 an array controller that applies control signals to control selector switches ([0131]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the control signals of the embodiments of Figs. 1, 9-10 and 16-17 to be applied by a controller as the embodiment of Fig. 21. It would have been obvious to one of ordinary skill in the art because it would have been applying a known technique (using a controller to apply control signals) to a known device (switching element controlled by control signals) ready for improvement to yield predictable results (using a controller to apply control signals to a switching element) for the benefit of using hardware to apply control signals to efficiently control switching elements (MPEP 2143, Example D).
The combination of Stewart and Li thus far does not disclose
wherein: the array of processing elements is configured to perform a multiplying accumulation nor first cache coefficients and/or input values of the multiplying accumulation.
Li discloses wherein: the array of processing elements is configured to perform a multiplying accumulation ([0089]) first cache coefficients and/or input values of the multiplying accumulation. ([0089 and 0103])
It would have been further obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the array of processing elements of Stewart to be able to perform multiply accumulate operations as the array of processor elements of Li. It would have been obvious to one of ordinary skill in the art because it would provide added flexibility and increased efficiency by allowing the array of processors to perform additional arithmetic operations (e.g. multiply accumulate operations).
In regards to claim 7, the combination of Stewart and Li discloses The computing device of claim 1 (see rejection of claim 1 above) comprising a plurality of caches connected to each processing element (Stewart: See Figs. 1-2: wherein a plurality of local memories are connected to each processor element via switching elements (Note: Li discloses the caches associated with PEs (See Li: Figs. 2-3A). Thus, the combination of references discloses the above limitations))
wherein each cache is associated with a different block of the memory cells. (Stewart: See Figs. 1-2 and [0040-0041]: wherein each of the local memories are associated with different segments of the memory array (Note: Li discloses the caches associated with different banks of memory (See Li: Figs. 2-3A). Thus, the combination of references discloses the above limitations))
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Abbo, PGPUB No. 2008/0320273 for teaching a SIMD processor comprising a plurality of processing elements, wherein each processing element has a dedicated memory portion and is able to access a different processing elements dedicated memory portion using a multiplexer
Skull, PGPUB No. 2003/0191922 for teaching a SIMD computer system comprising a plurality of processing elements each with a dedicated portion of an array of memory cells from an SRAM device
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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