DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 01/05/2026 has been considered and placed of record in the file.
Oath/Declaration
The Oath or Declaration is being considered by examiner and complies with PTO requirements.
Claim Objections
Claim 7 is objected to because of the following informalities:
Regarding claim 7, “(110b)” should be deleted in line 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi US 2025/0219604.
Consider claim 16, Choi discloses A data communication method (see FIG. 8) comprising:
generating, by a first semiconductor chip, a first clock signal (see FIG. 8 and ¶ [0071], wherein the system clock generation circuit 611 of the first semiconductor apparatus 610 may generate the system clock signal SCK i.e. first clock signal);
in response to the first clock signal, transmitting a first data signal to a second semiconductor chip as a second data signal (see FIG. 8 and ¶ [0072], wherein the data transmission circuit 612 transmit the data DQ i.e. first data signal, to a second semiconductor apparatus 620 in response to the system clock signal SCK);
sending the first clock signal as a second clock signal to the second semiconductor chip (see FIG. 8 and ¶ [0071], wherein the system clock SCK is provided to the second semiconductor apparatus 620 through clock bus 601);
receiving, by the second semiconductor chip, the second clock signal (see FIG. 8 and ¶ [0073], wherein the internal clock generation circuit 621 of second semiconductor apparatus 620 may receive system clock SCK that are transmitted through the clock bus 601);
in response to the second clock signal, transmitting a third data signal to the first semiconductor chip as a fourth data signal (see FIG. 8 and ¶ [0073-0074], wherein data transmission circuit 622 may transmit the data DQ to the first semiconductor apparatus 610 in response to the TCK clock signal derived from the system clock signal SCK); and
in response to a delayed version of the first clock signal, the first semiconductor chip receiving the fourth data signal (see FIG. 8, ¶ [0071-0072], wherein the system clock generation circuit 611 may delay the system clock signal SCK and provide the delayed clock signal to the data receiver circuit 613, in which the data receiver circuit 613 may receive the data DQ via bus 602).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi US 2025/0219604.
Consider claim 12, Choi discloses A semiconductor chip (see FIG. 8) comprising:
a clock signal source configured to generate a first clock signal (see FIG. 8 and ¶ [0071], wherein the system clock generation circuit 611 may generate system clock signal SCK);
a data signal transmitter configured to transmit a first data signal in response to the first clock signal (see FIG. 8 and ¶ [0072], wherein the data transmission circuit 612 may transmit data DQ in response to the system clock signal SCK);
a clock signal source configured to transmit the first clock signal (see FIG. 8 and ¶ [0071], wherein the system clock generation circuit 611 may transmit the system clock signal SCK); and
a data signal receiver configured to receive a second data signal in response to a delayed version of the first clock signal (see FIG. 8, ¶ [0071-0072], wherein the system clock generation circuit 611 may delay the system clock signal SCK and provide the delayed clock signal to the data receiver circuit 613, in which the data receiver circuit 613 may receive the data DQ).
Although Choi does not explicitly disclose a clock signal transmitter, Choi discloses system clock generation circuit 611 may transmit system clock signal SCK through the clock bus 601 (see FIG. 8 and ¶ [0071]); hence there would be a transmitter within the system clock generation circuit to be able to transmit the system clock SCK Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the invention of Choi to include a clock signal transmitter.
Consider claim 13, Choi discloses a delay circuit connected between the clock signal source and the data signal receiver and configured to generate a delayed version of the first clock signal, wherein the data signal receiver is configured to receive the second data signal in response to the delayed version of first clock signal (see FIG. 8 and ¶ [0071-0072], wherein the system clock generation circuit 611 includes delay-locked loop circuit configured to generate a delayed version of the system clock signal, and provide the delayed version of the system clock signal to the data receiver circuit 613).
Claim(s) 14 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi US 2025/0219604 as applied to claims 12 and 16 above, and further in view of Sekiya et al. US 2015/0229312.
Consider claim 14, Choi discloses every claimed limitation in claim 12.
Choi further discloses wherein the data signal receiver is configured to receive the second data signal in response to the delayed version of the first clock signal (see FIG. 8 and ¶ [0072])
However Choi does not explicitly disclose a delay circuit connected to the clock signal source and configured to generate a delayed version of the first clock signal; and a multiplexer connected between the delay circuit and the data signal receiver and configured to select the delayed version of the first clock signal and to forward the selected delayed version of the first clock signal to the data signal receiver. Sekiya teaches a delay circuit connected to the clock signal source and configured to generate a delayed version of the first clock signal (see FIG. 2 and ¶ [0045], wherein delay locked loop 400 configured to generate M delay clock signals); and a multiplexer connected between the delay circuit and the data signal receiver and configured to select the delayed version of the first clock signal and to forward the selected delayed version of the first clock signal to the data signal receiver (see FIG. 2 and ¶ [0048], wherein multiplexer 230 configured to select any one of the M delay clock signals). Sekiya further discloses reducing jitter in a clock signal (see ¶ [0006]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the invention of Choi, and to include a delay circuit connected to the clock signal source and configured to generate a delayed version of the first clock signal; and a multiplexer connected between the delay circuit and the data signal receiver and configured to select the delayed version of the first clock signal and to forward the selected delayed version of the first clock signal to the data signal receiver, as taught by Sekiya for the purpose of reducing jitter in a clock signal.
Claim 19 is rejected on the same ground as for claim 14 because of similar scope.
Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi US 2025/0219604 as applied to claim 16 above, and further in view of Narui US 2019/0304512.
Consider claim 18, Choi discloses every claimed limitation in claim 16.
However Choi does not explicitly disclose generating the delayed version of the clock signal by mimicking propagation delays of the first and second semiconductor chips. Narui teaches generating the delayed version of the clock signal by mimicking propagation delays of the first and second semiconductor chips (see ¶ [0016] and [0020]). Narui further discloses providing high data reliability, high speed of memory access, lower power consumption, and reducing chip size (see ¶ [0001]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the invention of Choi, and to include generating the delayed version of the clock signal by mimicking propagation delays of the first and second semiconductor chips, as taught by Narui for the purpose of providing high data reliability, high speed of memory access, lower power consumption, and reducing chip size.
Consider claim 20, Narui discloses introducing a propagation delay to the first clock signal substantially equal to a sum of a propagation delay introduced by the first and second semiconductor chips (see ¶ [0022-0025]).
Allowable Subject Matter
Claims 1-11 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1:
Claim 1 is drawn to A system comprising: a plurality of semiconductor chips stacked on top of each other and including first and second semiconductor chips, wherein the first semiconductor chip includes: a clock signal generating circuit configured to generate a first clock signal and a delayed version of the first clock signal; a transmitting circuit configured to transmit a first data signal in response to the first clock signal; and a receiving circuit configured to receive a second data signal in response to the delayed version of the first clock signal, wherein the receiving circuit is configured to receive the delayed version of the first clock signal at substantially the same time that the transmitting circuit is configured to receive the first clock signal. Closest prior art, Choi US 2025/0219604 in view of Fukaishi et al. US 2006/0001176, discloses A system comprising: a plurality of semiconductor chips stacked on top of each other and including first and second semiconductor chips, wherein the first semiconductor chip includes: a clock signal generating circuit configured to generate a first clock signal and a delayed version of the first clock signal; a transmitting circuit configured to transmit a first data signal in response to the first clock signal; and a receiving circuit configured to receive a second data signal in response to the delayed version of the first clock signal. However, prior art of record fails to disclose either alone or in combination the details of wherein the receiving circuit is configured to receive the delayed version of the first clock signal at substantially the same time that the transmitting circuit is configured to receive the first clock signal, as claimed in claim 1, in combination with each and every other limitation in the claim.
Regarding claims 2-11:
Claims 2-11 are allowed as being dependent on claim 1.
Claims 15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fukaishi et al. US 2006/0001176.
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/JANICE N TIEU/Primary Examiner, Art Unit 2633