DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 12-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-13 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. US 2025/0373239 in view of Choi US 2025/0219604.
Consider claim 12, Zhou discloses A semiconductor chip (see FIG. 1-2) comprising:
a clock signal source configured to generate a first clock signal (see FIG. 2 and ¶ [0051], wherein the first clock generation circuit 111 generates a first clock signal);
a data signal transmitter configured to transmit a first data signal via a first link (see FIG. 1 and ¶ [0046], wherein first transmitter 12 transmit first data signal via first link);
a clock signal transmitter configured to transmit the first clock signal (see FIG. 1 and ¶ [0046], wherein the first transmitter 12 transmits the first clock signal); and
a data signal receiver configured to receive a second data signal via a second link separate from the first link (see FIG. 1 and ¶ [0046], wherein the first transmitter/receiver 13 receives second data signal via a second link sperate from the first link).
However Zhou does not explicitly disclose transmit the first signal in response to the first clock signal; and receive the second signal in response to a delayed version of the first clock signal. Choi teaches transmit the first signal in response to the first clock signal (see FIG. 8 and ¶ [0072], wherein the data transmission circuit 612 may transmit data DQ in response to the system clock signal SCK); and receive the second signal in response to a delayed version of the first clock signal (see FIG. 8 and ¶ [0071-0072], wherein the system clock generation circuit 611 may delay the system clock signal SCK and provide the delayed clock signal to the data receiver 613, in which the data receiver circuit 613 may receive the data DQ). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the invention of Zhou, and to include transmit the first signal in response to the first clock signal; and receive the second signal in response to a delayed version of the first clock signal, as taught by Choi for the purpose of further disclosing the transmitter and receiver of the semiconductor as disclosed in Zhou using the same effective technique as the transmitter and receiver as discloses in Choi.
Claim 16 is rejected on the same ground as for claim 12 because of similar scope.
Consider claim 13, Choi discloses a delay circuit connected between the clock signal source and the data signal receiver and configured to generate a delayed version of the first clock signal, wherein the data signal receiver is configured to receive the second data signal in response to the delayed version of first clock signal (see FIG. 8 and ¶ [0071-0072], wherein the system clock generation circuit 611 includes delay-locked loop circuit configured to generate a delayed version of the system clock signal, and provide the delayed version of the system clock signal to the data receiver circuit 613).
Claim(s) 14 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. US 2025/0373239 in view of Choi US 2025/0219604 as applied to claims 12 and 16 above, and further in view of Sekiya et al. US 2015/0229312.
Consider claim 14, Zhou in view of Choi discloses every claimed limitation in claim 12.
Choi further discloses wherein the data signal receiver is configured to receive the second data signal in response to the delayed version of the first clock signal (see FIG. 8 and ¶ [0072])
However Zhou in view of Choi does not explicitly disclose a delay circuit connected to the clock signal source and configured to generate a delayed version of the first clock signal; and a multiplexer connected between the delay circuit and the data signal receiver and configured to select the delayed version of the first clock signal and to forward the selected delayed version of the first clock signal to the data signal receiver. Sekiya teaches a delay circuit connected to the clock signal source and configured to generate a delayed version of the first clock signal (see FIG. 2 and ¶ [0045], wherein delay locked loop 400 configured to generate M delay clock signals); and a multiplexer connected between the delay circuit and the data signal receiver and configured to select the delayed version of the first clock signal and to forward the selected delayed version of the first clock signal to the data signal receiver (see FIG. 2 and ¶ [0048], wherein multiplexer 230 configured to select any one of the M delay clock signals). Sekiya further discloses reducing jitter in a clock signal (see ¶ [0006]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the invention of Zhou in view of Choi, and to include a delay circuit connected to the clock signal source and configured to generate a delayed version of the first clock signal; and a multiplexer connected between the delay circuit and the data signal receiver and configured to select the delayed version of the first clock signal and to forward the selected delayed version of the first clock signal to the data signal receiver, as taught by Sekiya for the purpose of reducing jitter in a clock signal.
Claim 19 is rejected on the same ground as for claim 14 because of similar scope.
Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. US 2025/0373239 in view of Choi US 2025/0219604 as applied to claim 16 above, and further in view of Narui US 2019/0304512.
Consider claim 18, Zhou in view of Choi discloses every claimed limitation in claim 16.
However Zhou in view of Choi does not explicitly disclose generating the delayed version of the clock signal by mimicking propagation delays of the first and second semiconductor chips. Narui teaches generating the delayed version of the clock signal by mimicking propagation delays of the first and second semiconductor chips (see ¶ [0016] and [0020]). Narui further discloses providing high data reliability, high speed of memory access, lower power consumption, and reducing chip size (see ¶ [0001]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the invention of Zhou in view of Choi, and to include generating the delayed version of the clock signal by mimicking propagation delays of the first and second semiconductor chips, as taught by Narui for the purpose of providing high data reliability, high speed of memory access, lower power consumption, and reducing chip size.
Consider claim 20, Narui discloses introducing a propagation delay to the first clock signal substantially equal to a sum of a propagation delay introduced by the first and second semiconductor chips (see ¶ [0022-0025]).
Allowable Subject Matter
Claims 1-11 are allowed.
Claim 15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE N TIEU whose telephone number is (571)270-1888. The examiner can normally be reached Monday-Friday 9:00-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sam Ahn can be reached at (571) 272-3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JANICE N TIEU/Primary Examiner, Art Unit 2633
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