Prosecution Insights
Last updated: October 23, 2026
Application No. 18/919,634

DEVICES

Non-Final OA §102§DOUBLEPATENT
Filed
Oct 18, 2024
Priority
Sep 14, 2016 — provisional 62/394,225 +6 more
Examiner
CRAWFORD EASON, LATANYA N
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
79%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
732 granted / 933 resolved
+10.5% vs TC avg
Minimal +0% lift
Without
With
+0.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
38 currently pending
Career history
993
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
54.1%
+14.1% vs TC avg
§102
31.2%
-8.8% vs TC avg
§112
11.4%
-28.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 933 resolved cases

Office Action

§102 §DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Title The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1 & 5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, & 9 of U.S. Patent No. US Patent 12,148,740 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because: Claim 1, A device, comprising: a substrate; a plurality of semi-conductors disposed on the substrate, wherein each one of the plurality of semi-conductors comprises a P-type semi-conductor and an N-type semi-conductor; and an insulating layer disposed on the plurality of semi-conductors, wherein the insulating layer directly connects adjacent two of the plurality of semi-conductors( claim 1 or claim 9 of US Patent 12,148,740 B2). Claim 5, The device as claimed in claim 1, wherein the insulating layer has a sidewall profile in a cross-sectional view, and at least a part of the sidewall profile of the insulating layer is in a shape of a curve( 3 of US Patent 12,148,740 B2). . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okayama (US Pub no. 2012/0169786 A1) Regarding claim 1, Okayama et al discloses A device, comprising: substrate(210-1,[0123-0124], fig. 32/fig. 33 /fig, 15a/15b); a plurality of semi-conductors(10B,10R,10G,[0066][0127], fig. 32/fig.33/fig. 15a) disposed on the substrate(210-1,[0123-0124][0127], fig. 32/fig. 33 /fig, 15a/15b), wherein each one of the plurality of semi-conductors (10B,10R,10G,[[0066][0127], fig. 32/fig.33/fig. 15a)comprises a P-type semi-conductor and an N-type semi-conductor(Examiner notes that Okayama et al teaches a laminated structure in which a first conductivity type(11,[0066][0068], fig. 2, fig. 15a/15b) an active layer 12 and a second conductivity type(13,[0066][0068], fig. 2, fig. 15a/15b) are laminated in order therefore at least one of the conductivity types is P-type and at least one of the conductivity types is N- type); and an insulating layer (20, [0069-0070][0103], fig. 15a/fig. 15b)disposed on the plurality of semi-conductors(10B,10R,10G,[0066][0103][0127], fig. 32/fig.33/fig. 15a), wherein the insulating layer(20, [0069-0070][0103], fig. 15a/fig. 15b) directly connects adjacent two of the plurality of semi-conductors(10B,10R,10G,[0066][0127], fig. 32/fig.33/fig. 15a) Regarding claim 2, Okayama et al discloses further comprising a first electrode (30,[0073], fig. 15a/fig. 15b) disposed on a part of the N-type semi-conductor(11 or 13, fig 15a/15b)(Examiner notes that Okayama et al teaches a laminated structure in which a first conductivity type(11,[0066][0068], fig. 2, fig. 15a/15b) an active layer 12 and a second conductivity type(13,[0066][0068], fig. 2, fig. 15a/15b) are laminated, therefore at least one of the conductivity types is P-type and at least one of the conductivity types is N- type; since electrode 30 extends under and covers the side of light emitting element 10, the electrode is disposed on a part of the N-type semi-conductor fig. 15b) . Regarding claim 3, Okayama et al discloses wherein the first electrode (30,[0073], fig. 15a/15b)has a sidewall profile in a cross-sectional view, and at least a part of the sidewall profile of the first electrode(30,[0073][0103], fig. 15a/15b, insulating layer 20 has an inclined surface(20d) in a negative direction[0103], the electrode 30 is disposed on the base of 20 and conforms to the insulating layer(20) at the point where it rises, thereby forming a curved profile at the transition between the base and the inclined surface(20D)) is in a shape of a curve. Regarding claim 4, Okayama et al discloses wherein the insulating layer (20, [0070][0103], fig. 15a/fig. 15b)is disposed on the N-type semi-conductor, a part of the P-type semi-conductor)(Examiner notes that Okayama et al teaches a laminated structure in which a first conductivity type(11,[0066][0068], fig. 2, fig. 15a/15b) an active layer 12 and a second conductivity type(13,[0066][0068], fig. 2, fig. 15a/15b) are laminated, therefore at least one of the conductivity types is P-type and at least one of the conductivity types is N- type) and the first electrode(30,[0073], fig. 15a/15b). Regarding claim 5, Okayama et al discloses wherein the insulating layer (20, [0070][0103], fig. 15a/fig. 15b) has a sidewall profile in a cross-sectional view, and at least a part of the sidewall profile of the insulating layer(20, [0070][0103], fig. 15a/fig. 15b) is in a shape of a curve. Regarding claim 6, Okayama et al discloses further comprising a second electrode (40, [0073],fig. 15b)disposed on the insulating layer(20, [0070][0103], fig. 15a/fig. 15b) and in contact with the P-type semi- conductor(Examiner notes that Okayama et al teaches a laminated structure in which a first conductivity type(11,[0066][0068], fig. 2, fig. 15a/15b) an active layer 12 and a second conductivity type(13,[0066][0068], fig. 2, fig. 15a/15b) are laminated, therefore at least one of the conductivity types is P-type and at least one of the conductivity types is N- type, therefore electrode 40 is electrically in contact with the p-type semiconductor). Regarding claim 7, Okayama et al discloses wherein an upper surface of the insulating layer(20, [0070][0103], fig. 15a/fig. 15b) is lower than an upper surface of the second electrode(40, [0073],fig. 15b). Regarding claim 8, Okayama et al discloses wherein the second electrode(40, [0073],fig. 15b) further extends to a sidewall of the insulating layer(20, [0070][0103], fig. 15a/fig. 15b). Allowable Subject Matter Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. With regards to claim 9, the limitations of further comprising a connection structure comprising a second N-type semi-conductor, a third electrode, the insulating layer and a fourth electrode disposed on a non-display area of the substrate, wherein the third electrode is disposed on the second N-type semi-conductor, the insulating layer is disposed on the third electrode, and the fourth electrode is disposed on the insulating layer and in contact with the third electrode was not found in prior art. Claim 10 is objected to since it depends from claim 9. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Oct 18, 2024
Application Filed
Oct 15, 2026
Non-Final Rejection mailed — §102, §DOUBLEPATENT (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12745572
Memory Device Including Bottom Electrode Bridges and Method of Manufacture
4y 4m to grant Granted Sep 22, 2026
Patent 12740211
COMPONENT WITH IMPROVED CONNECTION STRUCTURE AND METHOD FOR PRODUCING A COMPONENT
3y 6m to grant Granted Sep 15, 2026
Patent 12740213
LED LIGHT SOURCE MODULE
3y 4m to grant Granted Sep 15, 2026
Patent 12733319
IMAGE DISPLAY DEVICE AND METHOD FOR MANUFACTURING IMAGE DISPLAY DEVICE
3y 6m to grant Granted Sep 08, 2026
Patent 12727291
DISPLAY DEVICE
3y 9m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
79%
With Interview (+0.4%)
2y 8m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 933 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month