DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on 08/14/2026 is acknowledged. The traversal is on the ground(s) that there is no serious burden to examine the entire application. This is not found persuasive because claim 18 is independent and comprises distinguished limitations of fabricating a plurality of memory dies, and programming the respective arrays of fuses of the plurality of memory dies with a respective delay state for initialization of each of the plurality of memory dies asynchronously..
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
IDS filed on 10/18/2024 is fully considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US Pub. 2018/0150100).
Regarding claim 1, Fig. 2 and Fig. 4 of Choi discloses a method, comprising:
receiving [by memory device 20, Fig. 1], by a memory device [20, Fig. 1], signaling indicative of a command [CMD, Fig. 1] to initialize a plurality of memory dies of the memory device [command signal CMD sends to memory device to start a memory operation including a initialization of an operation]; and
delaying [by circuit 700, Fig. 4], at a memory die [Fig. 4 is a delaying circuit of a memory die, of a plurality of memory dies as shows in Fig. 2] of the plurality of memory dies [CHIP0 to CHIP3] and based at least in part on fuse states of an array of fuses [fuse storages at 600, Fig. 4] of the memory die, initialization of the memory die by an amount of time relative to receipt of the signaling by the memory device [amount of delaying time of an initialization operation of a memory operation is relative to a command signal CMD because circuit 200 receives the CMD signal to generate PAT_WT and PAT_RD to generate delaying signal DLY_CODE, which is used by circuit 600 and 700 to generate a delayed signal].
Regarding claim 2, Fig. 2 and Fig. 4 of Choi discloses further comprising delaying, at a different memory die [Fig. 2 of Choi shows 4 different dies (CHIP0 to CHIP3, and each die has a delaying circuit as shows in Fig. 4] of the plurality of memory dies and based at least in part on fuse states [fuse states of storage 600, Fig. 4] of a different array of fuses of the different memory die, initialization of the different memory die by a different amount of time, relative to receipt of the signaling by the memory device [amount of delaying time of an initialization operation of a memory operation is relative to a command signal CMD because circuit 200 receives the CMD signal to generate PAT_WT and PAT_RD to generate delaying signal DLY_CODE, which is used by circuit 600 and 700 to generate a delayed signal].
Regarding claim 3, Fig. 4 of Choi discloses further comprising delaying, at a different memory die of the plurality of memory dies and based at least in part on fuse states of a different array of fuses of the different memory die [each die in Fig. 2 has a fuses 600 as shows in Fig. 4], initialization of the different memory die by the amount of time subsequent to initialization of the memory die [delaying time is adjusted by circuit 700 for memory operations including an initialization of a memory operation].
Regarding claim 4, Fig. 4 of Choi discloses wherein delaying the initialization of the memory die comprises programming the array of fuses so as to cause providing signaling associated with the initialization of the memory die to be delayed by the amount of time relative to receipt of the signaling by the memory device [fuse storage 600 is programmed to store delaying information].
Regarding claim 5, Fig. 4 of Choi discloses apparatus, comprising: a plurality of memory dies [CHIP0 to CHIP3, Fig. 2] each including a respective array of fuses [600, Fig. 4] and respective initialization circuitry [200]; and
a pin [CMD pin, Fig. 4] configured to receive signaling [CMD] indicative of a command to initialize the plurality of memory dies [CMD is to control to start a memory operation];
wherein the respective array of fuses [600, Fig. 4] is configured to cause a respective delay in providing the command [CMD] to the respective initialization circuitry by a respective amount of time relative to receipt of the command at the pin [amount of delaying time of an initialization operation of a memory operation is relative to a command signal CMD because circuit 200 receives the CMD signal to generate PAT_WT and PAT_RD to generate delaying signal DLY_CODE, which is used by circuit 600 and 700 to generate a delayed signal].
Regarding claims 6, 7, Fig. 4 of Choi discloses wherein the respective amount of time for at least one of the plurality of memory dies is different [each die has different delaying circuit as shows in Fig. 4. The delaying time is depending con CMD signal and PATs and PAT. Therefore, each die delaying is different].
Regarding claim 8, Fig. 4 of Choi discloses wherein the respective delay is based at least in part on fuse states [fuse states in circuit 600 controls delaying time generates by circuit 700] of the respective arrays of fuses.
Regarding claim 9, Fig. 2 and Fig. 4 of Choi discloses wherein a first subset of the plurality of memory dies [CHIP0 in Fig. 2] is coupled to a first command path [first path shows in Fig. 4] and a second subset of the plurality of memory dies [CHIP1] is coupled to a second command path [similar path as shows in Fig. 4]; wherein a first array of fuses [600, Fig. 4] of a first memory die [CHIP0] coupled to the first command path is configured to cause the respective delay of a first amount of time [amount of delay is relative to CMD, PAT, and fuse storage 600]; wherein a second array of fuses [each die has a circuit similar to 4. Therefore, the second die CHIP1 also has a second circuit as shows in Fig. 4] of a second memory die coupled to the first command path is configured to cause the respective delay of a second amount of time [second die can be configured to have second delay].
Regarding claims 10 and 11, Fig. 4 of Choi discloses wherein a third array of fuses [600 Fig. 4, for CHIP2 in Fig. 2] of a third memory die [CHIP2] coupled to the second command path [similar to Fig. 4] is configured to cause the respective delay of the first amount of time; wherein a fourth array of fuses of a fourth memory die [CHIP3] coupled to the second command path [similar to Fig. 4] is configured to cause the respective delay of the second amount of time [can be the same as the first amount of time].
Regarding claim 12, Fig. 4 of Choi discloses wherein the first subset comprises a first rank of a channel of a memory device [CHIP0, Fig. 2], and wherein the second subset comprises a second rank of the channel of the memory device [different channel for CHIP1].
Regarding claim 13, Fig. 2 of Choi discloses wherein the pin comprises a reset pin [CSE0].
Regarding claim 14, Fig. 2 of Choi discloses wherein the command comprises a reset command [CMDE].
Regarding claim 15, Fig. 2 of Choi discloses wherein the command comprises a powerup command [CSE].
Regarding claim 16, Fig. 1 of Choi discloses wherein the apparatus comprises a dynamic random access memory (DRAM) module [paragraph 0003].
Regarding claim 17, Fig. 2 of Choi discloses wherein the plurality of memory dies [CHIP0 to CHIP3] correspond to a channel of a memory device [channel connects to DQE].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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