DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim(s) 19-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/2/2026.
Applicant’s election without traverse of Species I, claims 1-18 in the reply filed on 6/2/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-6, 12-13 and 18 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20220069131 to Pesic (“Pesic”).
As to claim 1, Pesic teaches A three-dimensional, 3D (As found in at least FIGS. 4-11 and at least [0078]), ferroelectric memory structure (As found in at least the Abstract), comprising: a substrate (As found in at least [0048]); a layer stack arranged on the substrate, wherein the layer stack comprises a plurality of dielectric layers and first metallic layers, which are alternatingly arranged one on the other along a first axis (As found in at least FIGS. 4-11: dielectric SiO2 and metal layers alternating in the stack); a first ferroelectric layer extending through the layers of the stack (As found in at least FIG. 11 and [0064]: 1112); and a second metallic layer extending through the layers of the stack adjacent to the first ferroelectric layer (As found in at least FIG. 11 and [0064]: 1104); wherein the first ferroelectric layer forms, in combination with the plurality of first metallic layers and the second metallic layer, a plurality of first capacitive memory cells (As found in at least the Abstract, [0002], [0003], etc.); and wherein a first work function of the first metallic layers is different from a second work function of the second metallic layer (As found in at least the Abstract, [0002], [0003], etc.).
As to claim 2, Pesic teaches a second ferroelectric layer extending through the layers of the stack (As found in at least FIG. 11: 1114); and a third metallic layer extending through the layers of the stack adjacent to the second ferroelectric layer (As found in at least FIG. 11: 1106); wherein the second ferroelectric layer forms, in combination with the plurality of first metallic layers and the third metallic layer, a plurality of second capacitive memory cells (As found in at least the Abstract, [0002], [0003], etc.); and wherein the first work function of the first metallic layers is different from a third work function of the third metallic layer (As found in at least the Abstract, [0002], [0003], etc.).
As to claim 5, Pesic teaches wherein both the first ferroelectric layer and the second ferroelectric layer extend along the first axis or extend tilted at opposite angles with respect to the first axis (As found in at least FIG. 11: 1112 and 1114 extend at least along the first axis: vertically through the stack).
As to claim 6, Pesic teaches the first ferroelectric layer and the second ferroelectric layer are respectively electrically excitable to two polarization states; and each polarization state represents a memory state of respectively the first or second capacitive memory cells (As found in at least [0040]-[0042]).
As to claim 12, Pesic teaches wherein at least one of the first metallic layers, the second metallic layer, and the third metallic layer comprises any one of the following materials or material compositions: molybdenum; a composition comprising molybdenum and a molybdenum oxide; titanium nitride; a composition comprising ruthenium and titanium nitride; or tungsten (As found in at least [0054]: TiN).
As to claim 13, Pesic teaches wherein the first ferroelectric layer comprises hafnium-zirconium oxide, HZO, for example, lanthanum doped HZO (As found in at least [0062]).
As to claim 18, see rejection to at least claim 1; moreover, Pesic teaches in at least FIGS. 2, 4 wherein the 3D ferroelectric memory structures are arranged in a crossbar array.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220069131 to Pesic (“Pesic”) in view of U.S. Patent/Publication No. 20230054171 to Pesic et al. (“Pesic-2”).
As to claim 3, Pesic teaches substantially the claimed invention; yet the teachings may not expressly include: further comprising a dielectric material extending through the layers of the stack and arranged between the second metallic layer and the third metallic layer.
However, relevantly and complementarily, Pesic-2 teaches a dielectric material extending through the layers of the stack and arranged between the second metallic layer and the third metallic layer (As found in at least FIG. 10: two metal layers through the stack are separated by a dielectric material SiO2)
Pesic and Pesic-2 are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory devices that may include 3D ferroelectric memory devices.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Pesic as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Pesic-2 also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: Both Pesic and Pesic-2 teach dielectric material between metal layers extending through the stack; Pesic in at least FIG. 4 describes it, and Pesic-2 in at least FIG. 10 makes the arrangement even more clear; these metal layers are to be separated by some means so that to avoid metal-to-metal shorts.
Therefore, it would have been obvious to combine Pesic with Pesic-2 to make the above modification.
As to claim 4, Pesic teaches wherein both the first ferroelectric layer and the second ferroelectric layer extend along the first axis or extend tilted at opposite angles with respect to the first axis (As found in at least FIG. 11: 1112 and 1114 extend at least along the first axis: vertically through the stack).
Claim(s) 7-11 and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220069131 to Pesic (“Pesic”) in view of U.S. Patent/Publication No. 20260020251 to Huang et al. (“Huang”).
As to claim 7, at least Huang teaches wherein each first metallic layer of the plurality of first metallic layers is connected to a respective wordline driver (As found in at least FIGS. 1-2: ferroelectric cell 4 capped at one end with word line 2 and at the other end with bit line 3).
Pesic and Huang are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory devices that may include 3D ferroelectric memory devices.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Pesic as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Huang also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: a capacitor, including a ferroelectric capacitor, includes two electrical terminals, metal layers, that connect to source voltage/current to said capacitor; Huang teaches that one of these terminals may be a word line and the other a bit line; both word and bit lines well-known in the art as conductive traces that drive a memory cell.
Therefore, it would have been obvious to combine Pesic with Huang to make the above modification.
As to claim 8, Pesic teaches wherein each metallic layer of the second metallic layer and the third metallic layer is connected to a respective sensing circuit (As found in at least FIGS. 1-2: the output from a memory cell is connected to a neuron; which neuron connected to a current-carrying wire which is in turn coupled to a ferroelectric memory cell; FIG. 18A expands this disclosure by explicitly disclosing that the current-carrying wire is a bitline, and this bitline couples toa sensing circuit 1802).
As to claim 9, Pesic teaches wherein each sensing circuit is formed in the substrate (As found in at least FIG. 18A and at least [0081], 1802 is a sense amplifier, known in the art as built by transistors; this is similar to sensing circuit 41 in the instant Application which is also built by transistors, as found in at least [0071]).
As to claim 10, Pesic teaches wherein the first work function differs from the second work function and/or from the third work function by at least 0.3 eV (As found in at least [0054]: first work function of 4.5 eV, second work function of 5.6 eV).
As to claim 11, Pesic teaches wherein the first metallic layers comprise a different material or material composition than the second metallic layer and/or the third metallic layer (As found in at least [0054]: first metal TiN, second metal Pt).
As to claim 14, see rejection to at least claim 7.
As to claim 15, see rejection to at least claim 8.
As to claim 16, see rejection to at least claim 10.
As to claim 17, see rejection to at least claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights