Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/21/2024 & 11/05/2025 are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4, 7-10 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 line 3 recites the limitation “fault information". There is insufficient antecedent basis for this limitation in the claim.
Claim 4 line 1 recites “a target cache block”, There is insufficient antecedent basis for this limitation in the claim.
Claims 7-10 recite “a lowest fault severity”, There is insufficient antecedent basis for this limitation in the claim.
Any claim not specifically mentioned above, is objected due to its dependency on the objected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yigzaw et al., US 20210286667, hereinafter Yigzaw, in view of Du et al., "DPCLS: Improving Partial Cache Line Sparing with Dynamics for Memory Error Prevention", 2020 IEEE 38th International Conference on Computer Design (ICCD), hereinafter Du.
As per claim 1, Yigzaw teaches A memory fault processing method, wherein the method comprises:
obtaining, by an out-of-band controller (FIG.5, Plateform FW; Fig.1 Controller), fault information of a memory (FIG.5, Error logs...; Fig. 1, Memory 12), wherein the fault information indicates that at least one cache block is faulty; (FIG.5, FIG. 5 Error logs and identification data received; [0046] If other hardware resources such as a cache line sparing is available......)
determining a fault severity of a target cache block based on the fault information, wherein the target cache block is one of the at least one cache block;
(Fig. 5; [0043], UINT32 ErrorSeverity; [0050] a health coloring scheme;)
determining a target replacement cache block based on the fault severity of the target cache block, wherein the target replacement cache block is used to replace the target cache block, the target replacement cache block is a cache block that is currently used to replace a historically faulty cache block, (Fig. 5; [0054] memory footprint can be reclaimed) and
sending a repair request to a central processing unit CPU (FIG.5 OS), to request the CPU to perform fault repair on the target cache block, wherein the repair request carries mark information ([0043] Table, UINT8 Flags;) of the target replacement cache block. (FIG.5, “OS Maps out and informs platform FW for subsequent action”)
EXCEPT
the fault severity of the target cache block is greater than or equal to a fault severity of the historically faulty cache block; and
Du teaches
the fault severity of the target cache block is greater than or equal to a fault severity of the historically faulty cache block; and
(Du, Chap., III, Algorithm 2 Sparing directory management in DPCLS "if the error count of the nibble in the past 24 hours reaches the predefined threshold and the nibble is not in the directory, it is admitted by replacing the oldest nibble......")
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Yigzaw to incorporate the teaching of the elements as indicated above from Du, in order to provide simple or fast repairs (Yigzaw, [0001]).
As per claim 16, Yigzaw teaches A memory fault processing method, wherein the method comprises:
receiving, by a central processing unit (CPU) (FIG.5, OS; Fig.4 CPU HARDWARE 55 ; FIG.1, Host 15; ), a repair request sent by an out-of-band controller, (FIG.5, Notify OS with RAS Feature Table, Page map out action and proposal)
wherein the repair request requests to perform fault repair on a target cache block, the repair request carries mark information of a target replacement cache block, the target replacement cache block is a cache block that is currently used to replace a historically faulty cache block ([0054] memory footprint can be reclaimed), and
when an idle replacement cache block exists, replacing, by the CPU, the target cache block with the idle replacement cache block based on the repair request; or
when no idle replacement cache block exists, replacing, by the CPU, the target cache block with the target replacement cache block based on the repair request.
(FIG.5, OS Maps out and informs platform FW for subsequent action; [0043] Table, UINT8 Flags;)
EXCEPT
a fault severity of the target cache block is greater than or equal to a fault severity of the historically faulty cache block
Du teaches
a fault severity of the target cache block is greater than or equal to a fault severity of the historically faulty cache block
(Du, Chap., III, Algorithm 2 Sparing directory management in DPCLS "if the error count of the nibble in the past 24 hours reaches the predefined threshold and the nibble is not in the directory, it is admitted by replacing the oldest nibble......")
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Yigzaw to incorporate the teaching of the elements as indicated above from Du, in order to provide simple or fast repairs (Yigzaw, [0001]).
As per claim 2, Yigzaw-Du teaches the method as applied above in claim 1, Du further teaches wherein the determining of the fault severity of the target cache block based on the fault information comprises:
counting a fault occurrence quantity of the target cache block within a preset time period, wherein the fault occurrence quantity represents the fault severity of the target cache block, and the preset time period is a time period from a start-up of a server in which the memory is located to a current moment.
(Du, Chap., III, Algorithm 2 Sparing directory management in DPCLS "if the error count of the nibble in the past 24 hours reaches the predefined threshold and the nibble is not in the directory, it is admitted by replacing the oldest nibble......")
As per claim 3, Yigzaw-Du teaches the method as applied above in claim 1, Du further teaches wherein the determining of the fault severity of the target cache block based on the fault information comprises:
inputting fault information of the target cache block into a fault model, and receiving the fault severity of the target cache block as an output of the fault model, wherein the fault information comprises at least one of location information, a fault occurrence time, or a fault occurrence quantity.
(Du, Chap., III, Algorithm 2 Sparing directory management in DPCLS "if the error count of the nibble in the past 24 hours reaches the predefined threshold and the nibble is not in the directory, it is admitted by replacing the oldest nibble......")
As per claim 4, Yigzaw-Du teaches the method as applied above in claim 2, Du further teaches wherein the determining of the fault severity of a target cache block based on the fault information comprises:
inputting fault information of the target cache block into a fault model, and receiving the fault severity of the target cache block as an output of the fault model, wherein the fault information comprises at least one of location information, a fault occurrence time, and a fault occurrence quantity. (Du, Chap., III, Algorithm 2 Sparing directory management in DPCLS "if the error count of the nibble in the past 24 hours reaches the predefined threshold and the nibble is not in the directory, it is admitted by replacing the oldest nibble......")
As per claim 5, Yigzaw-Du teaches the method as applied above in claim 1, Yigzaw further teaches wherein the fault information comprises information about a location at which the at least one cache block is faulty, and before the determining of the fault severity of a target cache block based on the fault information, the method further comprises:
determining a fault type of the at least one cache block based on the information about the location at which the at least one cache block is faulty; and
determining that a cache block whose fault type is a single-point fault is the target cache block, wherein a row address of the target cache block is different from a row address of another faulty cache block, and a column address of the target cache block is different from a column address of the other faulty cache block. ([0030] at point A, the OS may maintain information for erroneous addresses in the memory subsystem 56, error counts, usage statistics, etc., and the OS may hen make offline decisions based on the maintained information.[0049]-[0056])
As per claim 6, Yigzaw-Du teaches the method as applied above in claim 2, Yigzaw further teaches wherein the fault information comprises information about a location at which the at least one cache block is faulty, and before the determining of the fault severity of a target cache block based on the fault information, the method further comprises:
determining a fault type of the at least one cache block based on the information about the location at which the at least one cache block is faulty; and
determining that a cache block whose fault type is a single-point fault is the target cache block, wherein a row address of the target cache block is different from a row address of another faulty cache block, and a column address of the target cache block is different from a column address of the other faulty cache block. ([0030] at point A, the OS may maintain information for erroneous addresses in the memory subsystem 56, error counts, usage statistics, etc., and the OS may hen make offline decisions based on the maintained information.[0049]-[0056])
As per claim 7, Yigzaw-Du teaches the method as applied above in claim 1, Du further teaches wherein the target replacement cache block is a cache block currently used to replace a historically faulty cache block with a lowest fault severity. (Du, Chap., III, Algorithm 2 Sparing directory management in DPCLS "if the error count of the nibble in the past 24 hours reaches the predefined threshold and the nibble is not in the directory, it is admitted by replacing the oldest nibble......")
As per claim 8, Yigzaw-Du teaches the method as applied above in claim 2, Du further teaches wherein the target replacement cache block is a cache block currently used to replace a historically faulty cache block with a lowest fault severity. (Du, Chap., III, Algorithm 2 Sparing directory management in DPCLS "if the error count of the nibble in the past 24 hours reaches the predefined threshold and the nibble is not in the directory, it is admitted by replacing the oldest nibble......")
As per claim 9, Yigzaw-Du teaches the method as applied above in claim 3, Du further teaches wherein the target replacement cache block is a cache block currently used to replace a historically faulty cache block with a lowest fault severity. (Du, Chap., III, Algorithm 2 Sparing directory management in DPCLS "if the error count of the nibble in the past 24 hours reaches the predefined threshold and the nibble is not in the directory, it is admitted by replacing the oldest nibble......")
As per claim 10, Yigzaw-Du teaches the method as applied above in claim 4, Du further teaches wherein the target replacement cache block is a cache block currently used to replace a historically faulty cache block with a lowest fault severity. (Du, Chap., III, Algorithm 2 Sparing directory management in DPCLS "if the error count of the nibble in the past 24 hours reaches the predefined threshold and the nibble is not in the directory, it is admitted by replacing the oldest nibble......")
As per claim 17, Yigzaw-Du teaches the method as applied above in claim 16, Du further teaches wherein the method further comprises:
sending, by the CPU, a fault repair result of the target cache block to the out-of-band controller; and
when the target cache block is replaced with the idle replacement cache block, and repair succeeds, sending information about the target cache block and the idle replacement cache block to the out-of-band controller; or
when the target cache block is replaced with the target replacement cache block, and repair succeeds, sending the mark information of the target replacement cache block to the out-of-band controller.
(Fig.5, OS completes the handshake; [0046])
As per claim 18, Yigzaw-Du teaches A memory fault processing apparatus, comprising a storage and a processor, as applied above in claim 1, Yigzaw further teaches wherein the storage is configured to store program code, and the processor is configured to invoke the program code to perform the method according to claims 1. (FIG.6, [0061] The cache 208 may store data (e.g., including instructions) that is utilized by one or more components of the processor 202-1, such as the cores 206.)
Claim(s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yigzaw et al., US 20210286667, hereinafter Yigzaw, in view of Du et al., "DPCLS: Improving Partial Cache Line Sparing with Dynamics for Memory Error Prevention", 2020 IEEE, Du, in further view of Bhavsar et al., US 6408401, hereinafter Bhavsar.
As per claim 11, Yigzaw-Du teaches the method as applied above in claim 1, EXCEPT wherein the method further comprises:
receiving a fault repair result of the target cache block sent by the CPU;
when the fault repair result indicates a repair success, storing, by the out-of-band controller, a correspondence between the target cache block and a replacement cache block that replaces the target cache block; and
when the fault repair result carries the mark information of the target replacement cache block, and indicates a repair success, updating, by the out-of-band controller, a correspondence between the target replacement cache block and the historically faulty cache block to a correspondence between the target replacement cache block and the target cache block.
Bhavsar teaches wherein the method further comprises:
receiving a fault repair result of the target cache block sent by the CPU;
when the fault repair result indicates a repair success, storing, by the out-of-band controller, a correspondence between the target cache block and a replacement cache block that replaces the target cache block; and
when the fault repair result carries the mark information of the target replacement cache block, and indicates a repair success, updating, by the out-of-band controller, a correspondence between the target replacement cache block and the historically faulty cache block to a correspondence between the target replacement cache block and the target cache block.
(Fig.6, 8:15-23, In step 518, V1 and the Must flags are set according to the Table 1 results from the Bitmap Update Logic 112. Row and column addresses of the faulty cell are stored in an entry if the corresponding updatex signal is asserted. If the RAM is found to be unrepairable by the Bitmap Update Logic 112, the Unrepairable flag 116 is set. In a preferred embodiment, testing continues even when the RAM is found to be unrepairable.
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Yigzaw-Du to incorporate the teaching of the elements as indicated above from Bhavsar, in order to provide simple or fast repairs (Yigzaw, [0001]).
Claims 12-15 have the same limitations as claim 11, therefore are rejected under the same reason as claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gilbertson et al., US 6594785, “System And Method For Fault Handling And Recovery In A Multi-processing System Having Hardware Resources Shared Between Multiple Partitions”
Jiang et al., “LIRS: An efficient low inter-reference recency set replacement policy to improve buffer cache performance,” in Proceedings of the 2002 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, ser. SIGMETRICS’02, 2002, pp. 31–42
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/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111