Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 9 and 14.
b. Claims 1-20 are pending on the application.
Drawings
The drawings were received on 10/21/2024. These drawings are review and accepted by examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1, 3-5, 7 and 9-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Narayanaswamy et al (Pub. No.: US 2012/0163109 A1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claims 1, Narayanaswamy et al in Figures 1-6 are directly discloses a memory device (a memory device 100, Fig. 1) comprising:
a memory array (a memory array 130AM, Fig. 1) including:
a plurality of bit cells (a plurality of bit cells 135B1….135AN, Fig. 1) arranged in an array of rows and columns and configured to store data (the plurality of bit cells 135B1…135AN coupled to bit line BL1..BLBN (row) and word line WORDLINE 125AM and 125A1 (column) and each of bit cell for stored data in memory, Fig. 1) therein;
a plurality of word lines (the plurality of word line WORDLINE 125AM and 125A1 (column) of memory cell 135B1) each connected to the bit cells in a respective row (the plurality of bit line (row) of memory cell 135B1, Fig. 1); and
a plurality of bit line pairs (the pair of bit line BL1, BLB1 and BLN, BLBN) each connected to the bit cells in a respective column (the bit cell 135A1 includes the bit line BL1, BLN and the word line WORDLINE 125AM and 125A1 (column), Fig. 1);
a plurality of sense amplifiers (a plurality of sense amplifier 160A1, 160AN, Fig. 4) each configured to amplify a voltage difference between a respective bit line pair in response to a sense amplifier enable signal (a signal ENSA), the voltage difference representing a bit stored in a bit cell (the bit cell 135A1, 135AN)(the sense amplifier 160A1, 160AN connected to the bit cell 135A, 135AN; respectively, includes the voltage apply to the bit cell during the operation, Fig. 1);
a plurality of tracking circuits (a tracking circuit 170, Fig. 1) connected to each of the sense amplifiers (the sense amplifier circuit 160A1, 160AN), each tracking circuit (the tracking circuit 170) configured to mimic a behavior of the memory array (the memory array 135A1….135AN) and to generate the sense amplifier enable signal (the signal ENSA) when activated; and
a tracking circuit activator (the tracking circuit 170) configured to activate the tracking circuits according to a predefined activation protocol that distributes workload between the tracking circuits (for example, the tracking circuit 170 connected to the plurality of memory cell 135A1…135AN through retention-till-access switch 165 and the sense amplifier circuit 150 for tracking the distributes wordload in memory array130AM, see at least in Fig. 4, paragraph 0013 to paragraph 0034 and the related disclosures).
Regarding dependent claims 3, Narayanaswamy et al in Figures 1-6 are directly discloses a memory device (a memory device 100, Fig. 1) further comprising: the tracking circuit (the tracking circuit 170) includes: a tracking bit line (the bit line BL1..BLBN); a tracking word line (the word line WORLIN 125AM, 125A1); and a plurality of tracking bit cells (the bit cell 135A..135AN) connected between the tracking bit line and the tracking word line; and a pseudo write driver (the wordline driver 120AM, 120A1) configured to receive a write enable signal (the enable signal VLK) and an internal clock signal (the enable signal WLJDR) and to drive the tracking bit line .
Regarding dependent claims 4, Narayanaswamy et al in Figures 1-6 are directly discloses a memory device (a memory device 100, Fig. 1) further comprising a multiplexer (the multiplexer circuit 155A1, 155AN, Fig. 1) connected between the pseudo write driver (the wordline driver 120AM, 120A1) and the tracking bit line and configured to selectively connect the pseudo write driver to the tracking bit line (the sense amplifier 150 includes the multiplexer 155A1, 155AN connected the memory array 130AM, Fig. 1).
Regarding dependent claims 5, Narayanaswamy et al in Figures 1-6 are directly discloses a memory device (a memory device 100, Fig. 1) further comprising a clock signal generator (the clock signal CLK) configured to generate an inverted version of the internal clock signal (the internal clock signa WLHDR).
Regarding dependent claims 7, Narayanaswamy et al in Figures 1-6 are directly discloses a memory device (a memory device 100, Fig. 1) further comprising a multiplexer (the multiplexer 155A1, 155AN) connected between the clock signal generator and the tracking bit line and configured to selectively connect the tracking bit line to the clock signal generator (the sense amplifier 150 includes the multiplexer 155A1, 155AN connected the memory array 130AM includes a plurality of bit line BL1…BLBN, Fig. 1).
Regarding to independent claims 9, Narayanaswamy et al in Figures 1-6 are directly discloses a memory device (a memory device 100, Fig. 1) comprising:
a plurality of memory arrays, each memory array (a memory array 130AM, Fig. 1) including:
a plurality of bit cells (a plurality of bit cells 135B1….135AN, Fig. 1) arranged in an array of rows and columns and configured to store data (the plurality of bit cells 135B1…135AN coupled to bit line BL1..BLBN (row) and word line WORDLINE 125AM and 125A1 (column) and each of bit cell for stored data in memory, Fig. 1) therein;
a plurality of word lines (the plurality of word line WORDLINE 125AM and 125A1 (column) of memory cell 135B1) each connected to the bit cells in a respective row (the plurality of bit line (row) of memory cell 135B1, Fig. 1); and
a plurality of bit line pairs (the pair of bit line BL1, BLB1 and BLN, BLBN) each connected to the bit cells in a respective column (the bit cell 135A1 includes the bit line BL1, BLN and the word line WORDLINE 125AM and 125A1 (column), Fig. 1);
a plurality of sense amplifiers (a plurality of sense amplifier 160A1, 160AN, Fig. 4) each configured to amplify a voltage difference between a respective bit line pair in response to a sense amplifier enable signal (a signal ENSA), the voltage difference representing a bit stored in a bit cell (the bit cell 135A1, 135AN)(the sense amplifier 160A1, 160AN connected to the bit cell 135A, 135AN; respectively, includes the voltage apply to the bit cell during the operation, Fig. 1); and
two or more tracking circuits (a tracking circuit 170, Fig. 1) connected to each of the sense amplifiers (the sense amplifier circuit 160A1, 160AN), each tracking circuit (the tracking circuit 170) configured to mimic a behavior of the memory array (the memory array 135A1….135AN) and to generate the sense amplifier enable signal (the signal ENSA) when activated; where a number of the tracking circuit is less or greater than a number of the memory arrays. (for example, the tracking circuit 170 connected to the plurality of memory cell 135A1…135AN through retention-till-access switch 165 and the sense amplifier circuit 150 for tracking the distributes wordload in memory array130AM, see at least in Fig. 4, paragraph 0013 to paragraph 0034 and the related disclosures).
Regarding dependent claims 10, Narayanaswamy et al in Figures 1-6 are directly discloses a memory device (a memory device 100, Fig. 1) further comprising: the tracking circuit (the tracking circuit 170) includes: a tracking bit line (the bit line BL1..BLBN); a tracking word line (the word line WORLIN 125AM, 125A1); and a plurality of tracking bit cells (the bit cell 135A..135AN) connected between the tracking bit line and the tracking word line (the wordline driver 120AM, 120A1) configured to receive a write enable signal (the enable signal VLK).
Regarding dependent claims 11, Narayanaswamy et al in Figures 1-6 are directly discloses a memory device (a memory device 100, Fig. 1) further comprising: a pseudo write driver (wordline driver 120AM, 120A1) configured to receive a write enable signal (the enable clock signal CLK) and an internal clock signal (the internal clock signal WLHDR) and to drive the tracking bit line (the bitline BL1..BLBN), and
a multiplexer (the multiplexer circuit 155A1, 155AN, Fig. 1) connected between the pseudo write driver (the wordline driver 120AM, 120A1) and the tracking bit line and configured to selectively connect the pseudo write driver to the tracking bit line (the sense amplifier 150 includes the multiplexer 155A1, 155AN connected the memory array 130AM, Fig. 1).
Regarding dependent claims 12, Narayanaswamy et al in Figures 1-6 are directly discloses a memory device (a memory device 100, Fig. 1) further comprising a clock signal generator (the clock signal CLK) configured to generate an inverted version of the internal clock signal (the internal clock signa WLHDR) and a sense amplifier enable signal generator configured to receive a combination of a trigger signal from the clock signal generator and a voltage signal on the tracking bit line and to generate a sense amplifier enable signal.
Regarding dependent claims 13, Narayanaswamy et al in Figures 1-6 are directly discloses a memory device (a memory device 100, Fig. 1) further comprising a clock signal (the clock signal CLK) generator configured to generate an internal clock signal (internal clock signal WLHDR); and a multiplexer (the multiplexer 155A1, 155AN) connected between the clock signal generator and the tracking word line and configured to selectively connect the tracking bit line to the clock signal generator to the tracking word line (the sense amplifier 150 includes the multiplexer 155A1, 155AN connected the memory array 130AM includes a plurality of bit line BL1…BLBN, Fig. 1).
Regarding claims 14-19, they encompass the same scope of invention as that of claims 1, 3-5 and 9-13, except they draft the invention in method format instead of apparatus format. Narayanaswamy et al teach all the necessary elements to perform the method of these claims. The aspects of the invention contained in claims 14-19, are therefore rejected in method format for the same reasons claims 1, 3-5 and 9-13, were rejected in apparatus format, as discussed above in the prior paragraphs of the office action.
Allowable Subject Matter
4. Claims 2, 6, 8 and 20 insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claim 2, the prior art fails to tech or suggest the claimed limitations, namely, the predefined activation protocol includes activating the tracking circuits sequentially, cyclically, randomly, pseudorandomly, alternately, in a clockwise pattern, in a counter-clockwise pattern, in a zigzag pattern, in an interlace manner, or combinations thereof.
With respected to dependent claim 6, the prior art fails to tech or suggest the claimed limitations, namely, a sense amplifier enable signal generator configured to receive a combination of a trigger signal from the clock signal generator and a voltage signal on the tracking bit line and to generate the sense amplifier enable signal.
With respected to dependent claim 8, the prior art fails to tech or suggest the claimed limitations, namely, a pre-charger connected between segments of the tracking bit line and configured to pre-charge the tracking bit line to a predetermined voltage level.
With respected to dependent claim 20, the prior art fails to tech or suggest the claimed limitations, namely, pre-charging segments of the tracking bit line to a predetermined voltage level.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Oh (US. 2005/0078542 A1) discloses memory device having multiple array structure for increased bandwidth.
Sung et al (US. 2003/0206448 A1) discloses sense amplifier enable signal generating circuit having process tracking capability and semiconductor memory device including the same.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights