DETAILED ACTION
This office action is in response to the application filed on 10/21/2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The present office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/21/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6, 8 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2022/0059503).
With respect to Claim 1, Kim shows (Fig. 7B) all aspects of the current invention including a semiconductor package comprising:
a semiconductor chip stack (410) including offset-stacked semiconductor chips (410-1 through 410-8)
a wiring layer (440) on the semiconductor chip stack;
a vertical conductive structure (420) connecting one of the semiconductor chips (410-1) to the wiring layer;
a molding layer (430) at least partially covering the semiconductor chip stack, and each side surface of the vertical conductive structures;
a passivation layer (442) between the wiring layer and the molding layer,
wherein the wiring layer includes a pad (444) in direct contact with the vertical conductive structure,
wherein the pad (444) is spaced apart from the molding layer with the passivation layer therebetween
With respect to Claim 2, Kim shows (Fig. 7B) wherein a width of the pad is greater than a width of the vertical conductive structure
With respect to Claim 6, Kim shows (Fig. 7B) wherein the passivation layer includes an insulating material different from a material of the molding layer
With respect to Claim 8, Kim shows (Fig. 7B) wherein the vertical conductive structure includes a vertical metal wire, or copper pillar, or both the metal wire and the metal pillar.
With respect to Claim 11, Kim shows (Fig. 7B) wherein a contact area between the vertical conductive structure and the pad is equal to the cross-sectional area of the vertical conductive structure.
Claims 1-2, 5-6, 8-12, 14-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh (US 10,861,826).
With respect to Claim 1, Oh shows (Fig. 22) all aspects of the current invention including a semiconductor package comprising:
a semiconductor chip stack (3) including offset-stacked semiconductor chips (31-38; see Fig 9)
a wiring layer (layer 1 comprising conductive wiring) on the semiconductor chip stack;
a vertical conductive structure (comprising layers 513a-513g; see Fig 6) connecting one of the semiconductor chips to the wiring layer;
a molding layer (7) at least partially covering the semiconductor chip stack, and each side surface of the vertical conductive structures;
a passivation layer (151) between the wiring layer and the molding layer,
wherein the wiring layer includes a pad (pad 131) in direct contact with the vertical conductive structure,
wherein the pad (444) is spaced apart from the molding layer with the passivation layer therebetween
With respect to Claim 2, Oh shows (Fig. 22) wherein a width of the pad is greater than a width of the vertical conductive structure
With respect to Claim 5, Oh shows (Fig. 22) wherein the vertical conductive structure extend through the molding layer and the passivation layer to the pad
With respect to Claim 6, Oh shows (Fig. 22) wherein the passivation layer includes an insulating material different from a material of the molding layer
With respect to Claim 8, Oh shows (Fig. 22) wherein the vertical conductive structure includes a vertical metal wire, or copper pillar, or both the metal wire and the metal pillar.
With respect to Claim 9, Oh shows (Fig. 11) an embodiment wherein the passivation layer includes a plurality of passivation layers (dielectric layers 511a-511g), wherein the molding layer defines a recess, and wherein the plurality of passivation layers are in the recess
With respect to Claim 10, Oh shows (Fig. 20) an embodiment wherein the vertical conductive structure includes a plurality of vertical conductive structures (layers 513a-513g), each connecting one of the semiconductor chips to the wiring layer, a molding layer (5,5’’) at least partially covering the semiconductor chip stack, and each side surface of the vertical conductive structures, wherein the molding layer includes a first portion in contact with side surfaces of the plurality of vertical conductive structures, and a second portion between ones of the plurality of vertical conductive structures (see 5’’; portions of the molding layer enclosed between the vertical conductive structures) and wherein a level of a lower surface of the first portion is lower than a level of a lower surface of the second portion.
With respect to Claim 11, Oh shows (Fig. 22) wherein a contact area between the vertical conductive structure and the pad is equal to the cross-sectional area of the vertical conductive structure
With respect to Claim 12, Oh shows (Fig. 11) all aspects of the current invention including a semiconductor package comprising:
a semiconductor chip stack (3) including offset-stacked semiconductor chips (31-38; see Fig 9)
a wiring layer (layer 1 comprising conductive wiring) spaced apart from the semiconductor chip stack;
a vertical conductive structure (5; comprising layers 513a-513g and layers 511a-511g; see Fig 5-6) connecting one of the semiconductor chips to the wiring layer;
a molding layer (7) at least partially covering the semiconductor chip stack, and each side surface of the vertical conductive structures;
wherein the vertical conductive structure includes a protruding portion (portion of layers 513a-513g that extend into layer 151) that extends from the molding layer toward the wiring layer
With respect to Claim 14, Oh shows (Fig. 11) wherein a side surface of the protruding portion is exposed from the molding layer.
With respect to Claim 15, Oh shows (Fig. 11) further comprising a passivation layer (151) at least partially covering the side surface of protruding portion, wherein the passivation layer includes an insulating material different from a material of the molding layer.
With respect to Claim 16, Oh shows (Fig. 11) wherein the molding layer includes an epoxy molding compound, and wherein the passivation layer includes a photo-imageable dielectric.
With respect to Claim 17, Oh shows (Fig. 11) wherein the vertical conductive structure includes a plurality of vertical conductive structures (layers 513a-513g), each connecting one of the semiconductor chips to the wiring layer, and wherein each of the plurality of vertical conductive structures includes a metal wire, a metal pillar, or both the metal wire and the metal pillar.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 10,861,826) in view of Appelt (US 2019/0006308)
With respect to Claim 3, Oh shows (Fig. 22) most aspects of the current invention including a semiconductor package comprising a pad in contact with the passivation layer. However, Oh does not show wherein the pad includes a seed pattern, and wherein the seed pattern is in contact with the passivation layer.
On the other hand, and in the same field of endeavor, Appelt teaches (Fig. 1) a semiconductor package comprising a semiconductor chip (2), a wiring layer (4) on the semiconductor chip, a vertical conductive structure (7) connecting the semiconductor chip to the wiring layer, wherein the wiring layer includes a passivation layer (82) and a pad (pad 4) in direct contact with the vertical conductive structure, wherein the pad includes a seed pattern (seed layer; par 78), and wherein the seed pattern is in contact with the passivation layer. Appelt teaches one of ordinary skill in the art would have known that the seed patterns are typically used in the semiconductor packaging industry to assist with providing electrical connections to electrical components.
Accordingly, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the pad includes a seed pattern, and wherein the seed pattern is in contact with the passivation layer in the device of Oh, because seed patterns are well-known in the semiconductor packaging industry for their use to assist with providing electrical connections to electrical components, as taught by Applet, and implementing an electrical connection structure for its conventional use would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007)
With respect to Claim 4, Appelt teaches (Fig. 10) wherein the seed pattern includes titanium.
Claims 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 10,861,826) in view of Chaung (US 9,716,080)
With respect to Claim 7, Oh shows (Fig. 22) most aspects of the current invention including a passivation layer between the wiring layer and the molding layer. However, Oh does not show wherein a thickness of the passivation layer is 0.1 µm to 2 µm.
On the other hand, and in the same field of endeavor, Chaung teaches (Fig. 1) a semiconductor package comprising a semiconductor chip stack (110) including offset-stacked semiconductor chips (111), a wiring layer (layer 150 comprising conductive wiring 151 and dielectric 153) on the semiconductor chip stack, a vertical conductive structure (132) connecting the semiconductor chip to the wiring layer, wherein the wiring layer includes a passivation layer (152) between the wiring layer and the molding layer, wherein a thickness of the passivation layer is 5 µm.
However, it is noted that the specification fails to provide teachings about the criticality of having a thickness of the passivation layer is 0.1 µm to 2 µm, as claimed in the instant application.
Regarding claim 7, the courts have held, differences in thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of having a thickness of the passivation layer is 0.1 µm to 2 µm, as claimed by the applicant, and similar arrangements are known in the art (see Chaung), it would have been obvious to one of the ordinary skill in the art to modify the arrangement in the device of Oh in view of Chaung.
Criticality: The specification contains no disclosure of either the critical nature of the claimed arrangement of thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 13, Oh shows (Fig. 22) most aspects of the current invention including a passivation layer 151, and further wherein the vertical conductive structure includes a protruding portion (portion of layers 513a-513g that extend into passivation layer 151). However, Oh does not show wherein the protruding portion extends 0.1 µm to 2 µm beyond the molding layer.
On the other hand, and in the same field of endeavor, Chaung teaches (Fig. 1) a semiconductor package comprising a semiconductor chip stack (110) including offset-stacked semiconductor chips (111), a wiring layer (layer 150 comprising conductive wiring 151 and dielectric 153) on the semiconductor chip stack, a vertical conductive structure (132) connecting the semiconductor chip to the wiring layer, wherein the wiring layer includes a passivation layer (152) between the wiring layer and the molding layer, wherein a thickness of the passivation layer is 5 µm.
However, it is noted that the specification fails to provide teachings about the criticality of having the protruding portion extends 0.1 µm to 2 µm beyond the molding layer, as claimed in the instant application.
Regarding claim 13, the courts have held, differences in the protruding portion ratio will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ratios are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of having the protruding portion extends 0.1 µm to 2 µm beyond the molding layer, as claimed by the applicant, and similar arrangements are known in the art (see Chaung), it would have been obvious to one of the ordinary skill in the art to modify the arrangement in the device of Oh in view of Chaung.
Criticality: The specification contains no disclosure of either the critical nature of the claimed ratio or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claims 18 are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 10,861,826) in view of Dominguez (US 2019/0229093)
With respect to Claim 18, Oh shows (Fig. 22) most aspects of the current invention including a vertical conductive structure. However, Oh does not show wherein a width of the metal wire is 30 µm or less, and wherein a width the metal pillar is a width of 50 µm or less.
On the other hand, and in the same field of endeavor, Dominguez teaches (Fig. 1) a semiconductor package comprising a semiconductor chip stack including offset-stacked semiconductor chips (120-124), a wiring layer (layer 110 comprising conductive wiring and dielectric) on the semiconductor chip stack, a vertical conductive structure (160-163) connecting the semiconductor chip to the wiring layer, wherein the vertical conductive structure includes a plurality of vertical conductive structures (160-163), each connecting one of the semiconductor chips to the wiring layer, and wherein each of the plurality of vertical conductive structures includes a metal wire, a metal pillar, or both the metal wire and the metal pillar and further wherein a wherein a width of the metal wire is 30 µm or less, and wherein a width the metal pillar is a width of 50 µm or greater.
However, it is noted that the specification fails to provide teachings about the criticality of having a width of the metal wire is 30 µm or less, and wherein a width the metal pillar is a width of 50 µm or less, as claimed in the instant application.
Regarding claim 18, the courts have held, differences in thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of having a width of the metal wire is 30 µm or less, and wherein a width the metal pillar is a width of 50 µm or less, as claimed by the applicant, and similar arrangements are known in the art (see Dominguez), it would have been obvious to one of the ordinary skill in the art to modify the arrangement in the device of Oh in view of Dominguez.
Criticality: The specification contains no disclosure of either the critical nature of the claimed arrangement of thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 10,276,545) in view of Chaung (US 9,716,080)
With respect to Claim 19, Huang shows (Fig. 1G) most aspects of the current invention including a semiconductor package comprising:
a support substrate (120)
a semiconductor chip stack (110) including offset-stacked semiconductor chips on the support substrate (120)
a wiring layer (layer 160 comprising conductive wiring 161) on the semiconductor chip stack
vertical conductive structures (132) connecting semiconductor chips to the wiring layer
a first molding layer (140) at least partially covering the semiconductor chip stack, and each side surface of the vertical conductive structures;
a passivation layer (162) between the wiring layer and the first molding layer
a dummy structure (50) on the support substrate;
a second molding layer (150) at least partially covering a side surface of the first molding layer, wherein the second molding layer between the dummy structure (50) and the passivation layer (162)
wherein the wiring layer includes a pad in contact with one of the vertical conductive structures and with the passivation layer
wherein the first molding layer includes an insulating material different from a material in the passivation layer, or the passivation layer (polyimide) includes an insulating material different from a material in the first molding layer (a semi-cured epoxy resin)
Furthermore, although Huang shows the dummy structure is removed from the chip structure in a final step of the device, Huang discloses it is not limited to that final step of the device.
On the other hand, and in the same field of endeavor, Chaung teaches (Fig. 4) a semiconductor package comprising a support substrate (121), a semiconductor chip stack (110) including offset-stacked semiconductor chips (111), a vertical conductive structure (132) connecting the semiconductor chip stack to a wiring layer (layer 150 comprising conductive wiring 151 and dielectric 153) on the semiconductor chip stack, a passivation layer (162) between the wiring layer and a molding layer (140), a dummy structure (280) on the support substrate, and the molding layer (140) between the dummy structure (280) and the passivation layer (162). Chaung teaches that the dummy structure is used to prevent exposure of the back of the chip and to provide resistance against stress generated during formation of the wiring layer structure, thereby achieving balance in package warpage.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the dummy structure removed from the chip structure in a final step of the device, or in the alternative, the dummy structure remaining on the support substrate in a final step of the device in the device of Huang, as taught by Chaung because the dummy structure is used to prevent exposure of the back of the chip and to provide resistance against stress generated during formation of the wiring layer structure, thereby achieving balance in package warpage.
With respect to Claim 20, Huang shows (Fig. 1G) wherein the passivation layer includes at least one of polyimide and benzocyclobutene (BCB).
Conclusion
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/Q. B./
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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