DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 11/14/2024.
Currently claims 10-18 are pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/21/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 12-13 and 16-18 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Claims 12 and 16 (frame vs. “the power module”)
Regarding claim 12, claim 10 recites “A power module, comprising” the first circuit carrier, the semiconductor elements and the T+ bridge and/or phase bridge “arranged in a first plane of a multifunctional frame,” i.e., the multifunctional frame is a part of the claimed power module. Claim 12 then recites that “the multifunctional frame is arranged above or below the power module.” A component cannot be located above or below the very assembly of which it is a part, so the spatial reference of claim 12 is indeterminate.
Regarding claim 16, “an arrangement including the multifunctional frame and the power module, which are in electrical contact with one another” likewise treats the frame and “the power module” as two separate bodies, contrary to claim 10. It is unclear what “the power module” denotes in claims 12 and 16.
For examination, “the power module” in claims 12 and 16 is read as the first circuit carrier together with the semiconductor elements mounted on it. Correction is required.
Claim 13 (antecedent basis)
Regarding claim 13, “the openings in the T+ bridge and/or the phase bridge” lacks antecedent basis. Claim 13 depends from claim 10, which recites no openings; openings are first introduced in claim 11. For examination, claim 13 is treated as depending from claim 11. Correction is required.
Claim 17 (term of degree)
Regarding claim 17, “forming a minimum distance from one another” is a term of degree. The specification refers only to a “minimal” or “smallest possible” distance, without any value, range or standard for measuring it (MPEP 2173.05(b)). One of ordinary skill cannot determine what spacing between the T+ bridge and the T- bridge is, or is not, “a minimum distance.” In addition, claim 10 recites “a T+ bridge and/or phase bridge” in the alternative, so when only the phase bridge is selected, “the T+ bridge” of claim 17 lacks antecedent basis. For examination, claim 17 is read as the T+ bridge and a T- bridge stacked one above the other and separated only by an insulating layer. Correction is required.
Claim 18 (“decoupled”; double inclusion)
Regarding claim 18, “in a manner decoupled from the first plane” is unclear. The semiconductor elements are expressly electrically contacted to the bridges in the first plane (claim 10), so “decoupled” cannot mean electrically decoupled, and the claim does not say whether mechanical, thermal or merely spatial decoupling is meant. Further, “a bottom of the power module” re-introduces the bottom already recited in claim 10, so it is unclear whether a second bottom is claimed. For examination, claim 18 is read as the semiconductor elements lying in the bottom plane, spatially separated from the first plane. Correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 10-15 and 17-18 under 35 U.S.C. 103 as unpatentable over Chen (US 2019/0287876 A1) in view of Hegedüs (US 2024/0145362 A1).
Regarding claim 10, Chen teaches, a power module (three-dimensional power-device packaging structure), comprising:
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“a first circuit carrier including a carrier substrate,” which is Chen’s DBC substrate with its aluminum-nitride ceramic intermediate layer (301; DBC substrate; Chen Fig. 5; [0093]).
“a first conductor structure having an external contact region,” which is Chen’s top-layer copper foil 305, soldered to FPC bottom foil 430 to form the positive electrode power terminal 11 (305; copper foil / positive electrode power terminal 11; Chen Figs. 5, 8-9; [0093], [0097]).
“at least one second conductor structure having at least one external contact region,” which is Chen’s top-layer copper foil 304, soldered to FPC foil 431 to form the output terminal 12 at the bridge-arm midpoint (304; copper foil / output terminal 12; Chen Figs. 5, 8; [0093], [0097]).
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“a first group of semiconductor elements and a second group of semiconductor elements,” which are Chen’s high-side MOSFET chips 20–25 with SBD chips 32–34 and low-side MOSFET chips 26–31 with SBD chips 35–37 (20–25, 26–31; MOSFET chips; Chen Fig. 8; [0096]).
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“wherein the first and second groups of semiconductor elements are arranged in a second plane at a bottom of the power module,” in that Chen’s chips are soldered on the top copper of the DBC substrates, which rest on the heat dissipation substrates 201–203 at the bottom of the structure (301–303, 201–203; DBC substrates, heat dissipation substrates; Chen Figs. 1–2; [0090], [0097]).
“are electrically contacted via bonding wires and/or at least one contact strip with a T+ bridge and/or phase bridge,” in that Chen’s bonding wire 51 connects the sources of high-side chips 20, 21 to FPC pads 415–417, which are connected by vias 433 to foil 431 forming the output (phase) terminal 12, i.e., a phase bridge (51, 415–417, 431; bonding wire, pads, copper foil / output terminal 12; Chen Figs. 6-8; [0097]).
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“arranged in a first plane of a multifunctional frame,” in that Chen’s FPC board 4 lies over the DBC substrates and frames each chip with a window. It carries the power loop, the decoupling-capacitor pads 418 and the laminated terminals 401–404, and its pads lie in a plane above the chip plane. Under the broadest reasonable interpretation, board 4 is a “multifunctional frame” (4, 405–410; FPC board, windows; Chen Figs. 6–7, 10; [0094], [0095], [0100]).
But Chen does not explicitly teach that the first circuit carrier further includes “a further, third conductor structure including an external contact region.” In Chen, the negative potential is carried by top foil 422 of the FPC board rather than by a third conductor section of the DBC substrate ([0097]).
However, in analogous art, Hegedüs teaches the following limitation: “a further, third conductor structure including an external contact region,” in that Hegedüs’s structured first metallization layer 111 of substrate 10 has three sections: 111₁ (AC output), 111₂ (DC+) and 111₃ (DC−). Each section is coupled to a bus bar 4 whose second end 42 extends outside the housing 7 as an external contact (111₁, 111₂, 111₃, 4; sections of first metallization layer, bus bars; Hegedüs Figs. 1, 4; [0024], [0025], [0034]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chen and Hegedüs before him/her, because giving each of the DC+, DC− and AC potentials its own substrate conductor section with its own external contact lets bus-bar positions be chosen to meet creepage-distance requirements and improve half-bridge switching behavior (Hegedüs [0035]). Absent this teaching in Chen, a person with ordinary skill in the art would be motivated to reach out to Hegedüs while forming the power module of Chen.
Regarding claim 11, the combination of Chen and Hegedüs teaches, the power module of claim 10, where Chen teaches:
“wherein the bonding wires and/or the at least one contact strip extend through openings of the T+ bridge or the phase bridge, to contact surfaces of the semiconductor elements,” in that Chen’s chips sit in windows 405–410 of FPC board 4, which carries the positive foil 430 and phase foil 431. The bonding wires 51, 52 run from the source electrodes (contact surfaces) of the chips up through those windows to the board pads (405–410, 51, 52; windows, bonding wires; Chen Figs. 6, 8; [0066], [0095], [0114]).
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Regarding claim 12, as best understood, the combination of Chen and Hegedüs teaches, the power module of claim 10, where Chen teaches:
“wherein the multifunctional frame is arranged above or below the power module as viewed in a Z direction,” in that Chen’s FPC board 4 is soldered on and lies above the DBC substrates carrying the chips (4, 301; FPC board, DBC substrate; Chen Figs. 1-2, 8; [0068], [0090]).
Regarding claim 13, as best understood (depending from claim 11), the combination of Chen and Hegedüs teaches, the power module, where Chen teaches:
“wherein a number of the openings in the T+ bridge and/or the phase bridge correspond to a number of semiconductor elements to be contacted,” in that Chen states that the number of windows in the FPC board is the same as the number of power devices (405–410; windows; Chen Fig. 6; [0081], [0104]).
Regarding claim 14, the combination of Chen and Hegedüs teaches, the power module of claim 10, where Chen teaches:
“wherein the bonding wires and/or the at least one contact strip are connected to connecting pads of the T+ bridge and/or a T- bridge,” in that Chen’s bonding wire 52 connects the low-side sources to pads 419-421, which belong to top-layer foil 422 forming the negative electrode power terminal 13 (a T- bridge) (52, 419–421, 422; bonding wire, pads, copper foil / negative terminal 13; Chen Figs. 6, 8; [0097]).
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Regarding claim 15, the combination of Chen and Hegedüs teaches, the power module of claim 10, where Chen teaches:
“wherein the power module is connected to a cooling surface: (i) via a flat sintered connection or (ii) via a flat solder/adhesive connection,” in that Chen’s DBC substrates are soldered face-to-face onto heat dissipation substrates 201–203 with screen-printed Pb37/Sn63 solder paste, and those substrates are screwed to heatsink 1 (201–203, 1; heat dissipation substrates, heatsink; Chen Figs. 3–4; [0087], [0116]).
Hegedüs likewise teaches a solder or sintered connection layer 30 (Hegedüs [0024]).
Regarding claim 17, as best understood, the combination of Chen and Hegedüs teaches, the power module of claim 10, where Chen teaches:
“wherein the T+ bridge and a T- bridge are accommodated one above the other in the first plane of the multifunctional frame, forming a minimum distance from one another,” in that Chen’s FPC board 4 has a three-layer structure. Its bottom copper 430 (positive, T+) and top copper 422 (negative, T-) are stacked on either side of a thin polyimide insulating layer, whose thickness “can be greatly reduced,” enhancing mutual-inductance cancellation. The same stack forms laminated busbars 401–403 (430, 422, 401–403; bottom/top copper foils, stacked busbar structures; Chen Figs. 6-7, 10; [0060], [0067], [0075], [0100]).
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Regarding claim 18, as best understood, the combination of Chen and Hegedüs teaches, the power module of claim 10, where Chen teaches:
“wherein a bottom of the power module forms the second plane in which the semiconductor elements are arranged in a manner decoupled from the first plane,” in that Chen’s chips are attached directly to the DBC substrate at the bottom of the structure through the FPC windows, spatially separate from the upper pad plane of FPC board 4 and connected to it only by bonding wires (301, 405–410; DBC substrate, windows; Chen Figs. 5–8; [0066], [0068]).
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Claim 16 under 35 U.S.C. 103 as unpatentable over Chen (US 2019/0287876 A1) in view of Hegedüs (US 2024/0145362 A1), and further in view of Chi (US 2024/0170378 A1).
Regarding claim 16, as best understood, the combination of Chen and Hegedüs teaches, the power module of claim 10. Chen teaches that the frame (FPC board 4) and the DBC/chip assembly, which are in electrical contact with one another, are enclosed by shells 111–113 filled with silicone gel through a hole 7 (Chen [0091]).
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But Chen does not expressly teach that the enclosure is “a molding compound that includes one or more access openings.”
However, in analogous art, Chi teaches the following limitation:
“is enclosed by a molding compound that includes one or more access openings,” in that Chi’s mold body 150 of epoxy molding compound encapsulates the die 110, substrate 112 and lead frames 120, 130, and includes a through-mold via 160 that leaves the plated-through hole 162 exposed and accessible from outside (150, 160; mold body, through-mold via; Chi Figs. 1A–1C; [0017], [0018], [0023], [0025]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chen, Hegedüs and Chi before him/her, because a rigid epoxy mold body protects the assembly mechanically, and its access openings allow reliable, solderless external connection without stress cracking of the molding compound (Chi [0018], [0020]). Absent this teaching in Chen, a person with ordinary skill in the art would be motivated to reach out to Chi while forming the power module of Chen.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
1. Ewald (US 2024/0038639 A1) - lead frame arranged above power semiconductors on a DBC substrate, with an insulating carrier element carrying gate/Kelvin tracks wire-bonded to the chips, and potting compound.
2. Kim (US 2023/0395514 A1) - power module with a patterned second insulation layer and upper conductive segments whose gaps expose die-attach pads, allowing bond wires to pass to the dies; mold compound 313.
3. Endres (US 2024/0379573 A1) - insulating substrate with first, second and third conductor tracks, parallel chips bond-connected to a conductor track leading to a busbar connection element; sintered/soldered to a heatsink.
4. Komatsu (US 2024/0072030 A1) - half-bridge module with separate DC+, AC and DC− lead frames on one DBC substrate, interconnected by conductor tracks and bonding wires.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
09/29/2026
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