DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 10/21/24 are acceptable.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-7, 13-15 and 18-20 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-7 and 9-10 of prior U.S. Patent No. 12,166,421. This is a statutory double patenting rejection.
Application No. 18/922,179
U.S. Patent No. 12,166,421
Claim 1. A circuit comprising: a first switch coupled between a power input node and a first terminal of a load; a first current sense device arranged to transmit a first signal including at least one of a magnitude or a polarity of a first current through the first switch, wherein the first current sense device comprises a second switch coupled in parallel with the first switch; and a first driver circuit arranged to transmit first control signals to the first switch based at least in part on a voltage at the power input node and the first signal.
Claim 1. A circuit comprising: a first switch coupled between a power input node and a first terminal of a load; a first current sense device arranged to transmit a first signal including at least one of a magnitude and polarity of a first current through the first switch, wherein the first current sense device comprises a second switch coupled in parallel with the first switch; and a first driver circuit arranged to transmit first control signals to the first switch based at least in part on a voltage at the power input node and the first signal.
Claim 2. The circuit of claim 1, wherein the first driver circuit comprises a first threshold generation circuit, and wherein the first threshold generation circuit is arranged to generate a first threshold signal based on the voltage at the power input node.
Claim 5. The circuit of claim 3, wherein the first driver circuit comprises a first threshold generation circuit and the second driver circuit comprises a second threshold generation circuit.
Claim 6. The circuit of claim 5, wherein the first threshold generation circuit is arranged to generate a first threshold signal based on the voltage at the power input node.
Claim 3. The circuit of claim 2, further comprising: a third switch coupled between the power input node and a second terminal of the load; a second current sense device arranged to transmit a second signal including at least one of a magnitude or a polarity of a second current through the third switch; and a second driver circuit arranged to transmit second control signals to the third switch based at least in part on the voltage at the power input node and the second signal.
Claim 3. The circuit of claim 1, further comprising: a third switch coupled between the power input node and a second terminal of the load; a second current sense device arranged to transmit a second signal including at least one of a magnitude and polarity of a second current through the third switch; and a second driver circuit arranged to transmit second control signals to the third switch based at least in part on the voltage at the power input node and the second signal.
Claim 4. The circuit of claim 3, the first and second switches are a gallium nitride (GaN)- based switches.
Claim 2. The circuit of claim 1, wherein the first switch is a gallium nitride (GaN) based switch.
Claim 5. The circuit of claim 4, wherein
the third switch is GaN-based switch.
Claim 4. The circuit of claim 3, wherein the third switch is a gallium nitride (GaN) based switch.
Claim 6. The circuit of claim 5, wherein a value of the first threshold signal is based on a duty cycle of a pulse width modulated (PWM) signal received from a controller.
Claim 7. The circuit of claim 6, wherein a value of the first threshold signal is based on a duty cycle of a pulse width modulated (PWM) signal received from a controller.
Claim 7. The circuit of claim 6, wherein the value of the first threshold signal is high when the duty cycle of the PWM signal is high.
Claim 7. The circuit of claim 6, wherein a value of the first threshold signal is based on a duty cycle of a pulse width modulated (PWM) signal received from a controller.
Claim 13. A circuit comprising: a first switch coupled between a power input node and a first terminal of a load; a first current sense device arranged to transmit a first signal including a magnitude of a first current through the first switch, wherein the first current sense device comprises a second switch coupled in parallel with the first switch; and a first driver circuit arranged to transmit control signals to the first switch based at least in part on a voltage at the power input node and the first signal.
Claim 1. A circuit comprising: a first switch coupled between a power input node and a first terminal of a load; a first current sense device arranged to transmit a first signal including at least one of a magnitude and polarity of a first current through the first switch, wherein the first current sense device comprises a second switch coupled in parallel with the first switch; and a first driver circuit arranged to transmit first control signals to the first switch based at least in part on a voltage at the power input node and the first signal.
Claim 14. The circuit of claim 13, wherein the first driver circuit comprises a first threshold generation circuit, and wherein the first threshold generation circuit is arranged to generate a first threshold signal based on the voltage at the power input node.
Claim 5. The circuit of claim 3, wherein the first driver circuit comprises a first threshold generation circuit and the second driver circuit comprises a second threshold generation circuit.
Claim 6. The circuit of claim 5, wherein the first threshold generation circuit is arranged to generate a first threshold signal based on the voltage at the power input node.
Claim 15. The circuit of claim 14, further comprising: a third switch coupled between the power input node and a second terminal of the load; a second current sense device arranged to transmit a second signal including a magnitude of a second current through the third switch; and a second driver circuit arranged to transmit second control signals to the third switch based at least in part on the voltage at the power input node and the second signa
Claim 3. The circuit of claim 1, further comprising: a third switch coupled between the power input node and a second terminal of the load; a second current sense device arranged to transmit a second signal including at least one of a magnitude and polarity of a second current through the third switch; and a second driver circuit arranged to transmit second control signals to the third switch based at least in part on the voltage at the power input node and the second signal.
Claim 18. The circuit of claim 14, wherein a value of the first threshold signal is based on a duty cycle of a pulse width modulated (PWM) signal received from a controller.
Claim 7. The circuit of claim 6, wherein a value of the first threshold signal is based on a duty cycle of a pulse width modulated (PWM) signal received from a controller.
Claim 19. The circuit of claim 18, wherein the value of the first threshold signal is high when the duty cycle of the PWM signal is high.
Claim 9. The circuit of claim 7, wherein the value of the first threshold signal is low when the duty cycle of the PWM signal is low.
Claim 20. The circuit of claim 19, wherein the first driver circuit further comprises a first comparator arranged receive the first threshold signal, and wherein the first comparator is further arranged to compare the first signal to the first threshold signal and generate a first current detection signal.
Claim 10. The circuit of claim 6, wherein the first driver circuit further comprises a first comparator arranged receive the first threshold signal, and wherein the first comparator is further arranged to compare the first signal to the first threshold signal and generate a first current detection signal.
Allowable Subject Matter
Claims 8-12 are allowed over the cited prior.
Claims 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 6/26/26 have been fully considered but they are not persuasive. Terminal disclaimer filed on 6/26/26 has been approved. Applicant has not amended the claims.
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7 AM - 10 PM.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838
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