DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the claims filled on 10/22/2024 that has been entered, wherein claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/22/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation of “the plating pattern is exposed by the plating pattern” in line 2. How can an element expose itself? For the purpose of examination, “the plating pattern is exposed by the plating pattern” will be interpreted as “the seed layer pattern is exposed by the plating pattern”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7, 9 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pun et al. (US 2018/0102312 A1) in view of Jung et al. (US 6,333,252 B1).
Regarding claim 1, Pun teaches a semiconductor package(Fig. 6, Fig. 9, ¶0035), comprising:
a package substrate(10) including a mounting region(region with 50) and a peripheral region(region surrounding 50) surrounding the mounting region(region with 50), the package substrate(10) having a plurality of bonding fingers(24, ¶0034) on the peripheral region(region surrounding 50) on an upper surface of the package substrate(10);
a semiconductor chip(50, ¶0034) disposed on the mounting region(region with 50) of the package substrate(10), the semiconductor chip(50, ¶0034) having a first surface, and a second surface that is opposite to the first surface and faces the package substrate(10);
a plurality of bonding wires(52, ¶0034) electrically connecting the semiconductor chip(50, ¶0034) and the plurality of bonding fingers(24, ¶0034),
wherein each of the plurality of bonding fingers(24, ¶0034) comprises:
a seed layer pattern(12, ¶0038) disposed on the upper surface in the peripheral region(region surrounding 50) of the package substrate(10), the seed layer pattern(12, ¶0038) having a first region(upper surface) and a second region(vertical side surfaces) surrounding the first region(upper surface);
a finger body(16, ¶0040) on the first region(upper surface) of the seed layer pattern(12, ¶0038) and having a predetermined thickness; and
a plating pattern(18,20, 22, ¶0041-43) having a first plating portion(horizontal portion of 18,20, 22, ¶0041-43) and a second plating portion(vertical portion of 18,20, 22, ¶0041-43), wherein the first plating portion(horizontal portion of 18,20, 22, ¶0041-43) covers an upper surface of the finger body(16, ¶0040), and the second plating portion(vertical portion of 18,20, 22, ¶0041-43) covers a side surface of the finger body(16, ¶0040) and contacts the second region(vertical side surfaces) of the seed layer pattern(12, ¶0038), and
wherein for each bonding finger(24, ¶0034) from the plurality of bonding fingers(24, ¶0034), one end of a bonding wire(52, ¶0034) from the plurality of bonding wires(52, ¶0034), is bonded to an upper surface of the plating pattern(18,20, 22, ¶0041-43).
Pun is not relied on to teach the semiconductor chip(50, ¶0034) having a first surface where chip pads are formed, a plurality of bonding wires(52, ¶0034) electrically connecting the chip pads and the plurality of bonding fingers(24, ¶0034).
Jung teaches a semiconductor package(Fig. 2) wherein the semiconductor chip(210, col. 3, lines 34-37) having a first surface where chip pads(210a, col. 2, line 54-col. 3, line 4) are formed, a plurality of bonding wires(212, col. 2, line 54-col. 3 , line 4) electrically connecting the chip pads(210a, col. 2, line 54-col. 3, line 4) and the plurality of bonding fingers(230, col. 2, line 54-col. 3, line 4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Pun, so that semiconductor chip having a first surface where chip pads are formed, a plurality of bonding wires electrically connecting the chip pads and the plurality of bonding fingers, as taught by Jung, in order to connect the active surface of the chip via the chip pads(col. 2, line 54-col. 3, line 4).
Regarding claim 2, Pun teaches the semiconductor package of claim 1, wherein the upper surface of the plating pattern(18,20, 22, ¶0041-43) and a side surface of the plating pattern(18,20, 22, ¶0041-43) meet at a predetermined angle at an angled edge of the upper surface and the side surface(90°, Fig. 9).
Regarding claim 3, Pun teaches the semiconductor package of claim 2, wherein the predetermined angle is 85-95 degrees(90°, Fig. 9).
Regarding claim 4, Pun teaches the semiconductor package of claim 1, wherein the finger body(16, ¶0040) includes copper (Cu)(¶0040).
Regarding claim 5, Pun teaches the semiconductor package of claim 1,
wherein the plating pattern(18,20, 22, ¶0041-43) includes a first plating pattern layer(20, ¶0041) and a second plating pattern layer(22, ¶0043) on the first plating pattern layer(20, ¶0041), and
wherein the first plating pattern layer(20, ¶0041) includes nickel (Ni)(¶0041), and the second plating pattern layer(22, ¶0043) includes gold (Au)(¶0043).
Regarding claim 6, Pun teaches the semiconductor package of claim 5,
wherein the finger body(16, ¶0040) has a thickness within a range of 5 μm to 30 μm(¶0040),
wherein the first plating pattern layer(20, ¶0041) has a thickness within a range of 1 μm to 15 μm(¶0041),
wherein the second plating pattern layer(22, ¶0043) has a thickness within a range of 0.1 μm and 1.5 μm(¶0043).
Regarding claim 7, Pun teaches the semiconductor package of claim 1, wherein the plurality of bonding fingers(24, ¶0034) having a rectangular(Fig. 6) or elliptical planar shape.
Regarding claim 9, Pun teaches the semiconductor package of claim 1, wherein a side surface of the plating pattern(18,20, 22, ¶0041-43) extends at an angle of 85-95 degrees(90°, Fig. 9) with respect to an upper surface of the seed layer pattern(12, ¶0038).
Regarding claim 11, Pun teaches a semiconductor package(Fig. 6, Fig. 9, ¶0035) comprising:
a package substrate(10) having a plurality of bonding fingers(24, ¶0034) on an upper surface of the package substrate(10);
a semiconductor chip(50, ¶0034) disposed on the upper surface of the package substrate(10), the semiconductor chip(50, ¶0034) having a first surface, and a second surface that is opposite to the first surface and faces the package substrate(10); and
a plurality of bonding wires(52, ¶0034) electrically connecting the semiconductor chip(50, ¶0034) and the plurality of bonding fingers(24, ¶0034),
wherein each of the plurality of bonding fingers(24, ¶0034) comprises:
a seed layer pattern(12, ¶0038) disposed on the upper surface of the package substrate(10), the seed layer pattern(12, ¶0038) having a first region(upper surface) and a second region(vertical side surfaces) surrounding the first region(upper surface);
a finger body(16, ¶0040) on the first region(upper surface) of the seed layer pattern(12, ¶0038) and having a predetermined thickness; and
a plating pattern(18,20, 22, ¶0041-43) covering an upper surface of the finger body(16, ¶0040) and contacting the second region(vertical side surfaces) of the seed layer pattern(12, ¶0038), and
wherein for each bonding finger from the plurality of bonding fingers(24, ¶0034), one end of a bonding wire from the plurality of bonding wires(52, ¶0034), is bonded to an upper surface of the plating pattern(18,20, 22, ¶0041-43).
Pun is not relied on to teach the semiconductor chip(50, ¶0034) having a first surface where chip pads are formed, a plurality of bonding wires(52, ¶0034) electrically connecting the chip pads and the plurality of bonding fingers(24, ¶0034).
Jung teaches a semiconductor package(Fig. 2) wherein the semiconductor chip(210, col. 3, lines 34-37) having a first surface where chip pads(210a, col. 2, line 54-col. 3, line 4) are formed, a plurality of bonding wires(212, col. 2, line 54-col. 3 , line 4) electrically connecting the chip pads(210a, col. 2, line 54-col. 3, line 4) and the plurality of bonding fingers(230, col. 2, line 54-col. 3, line 4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Pun, so that semiconductor chip having a first surface where chip pads are formed, a plurality of bonding wires electrically connecting the chip pads and the plurality of bonding fingers, as taught by Jung, in order to connect the active surface of the chip via the chip pads(col. 2, line 54-col. 3, line 4).
Regarding claim 12, Pun teaches the semiconductor package of claim 11, wherein the upper surface of the plating pattern(18,20, 22, ¶0041-43) and a side surface of the plating pattern(18,20, 22, ¶0041-43) meet at a predetermined angle(90°, Fig. 9) at an angled edge of the upper surface and the side surface.
Regarding claim 13, Pun teaches the semiconductor package of claim 12, wherein the predetermined angle is 85-95 degrees(90°, Fig. 9).
Regarding claim 14, Pun teaches the semiconductor package of claim 11, wherein a side surface of the plating pattern(18,20, 22, ¶0041-43) extends at an angle of 85-95 degrees(90°, Fig. 9) with respect to the upper surface of the seed layer pattern(12, ¶0038).
Regarding claim 15, Pun teaches the semiconductor package of claim 11, wherein the finger body(16, ¶0040) includes copper (Cu)(¶0040).
Regarding claim 16, Pun teaches the semiconductor package of claim 11, wherein the plating pattern(18,20, 22, ¶0041-43) includes a first plating pattern layer(20, ¶0041) and a second plating pattern layer(22, ¶0043) on the first plating pattern layer(20, ¶0041).
Regarding claim 17, Pun teaches the semiconductor package of claim 16, wherein the first plating pattern layer(20, ¶0041) includes nickel (Ni)(¶0041) and, the second plating pattern layer(22, ¶0043) includes gold(Au)(¶0043).
Regarding claim 18, Pun teaches the semiconductor package of claim 16, wherein the finger body(16, ¶0040) has a thickness of 5μm to 30μm(¶0040), wherein the first plating pattern layer(20, ¶0041) has a thickness of 1μm to 15μm(¶0041), and wherein the second plating pattern layer(22, ¶0043) has a thickness of 0.1μm to 1.5μm(¶0043).
Regarding claim 19, Pun teaches the semiconductor package of claim 11, wherein the package substrate(10) further comprises an upper protection layer(34, ¶0045) having openings that expose the plurality of bonding fingers(24, ¶0034) on the upper surface of the package substrate(10).
Regarding claim 20, Pun teaches a semiconductor package(Fig. 6, Fig. 9, ¶0035), comprising:
a package substrate(10) including an upper protection layer(34, ¶0045) having openings that expose a plurality of bonding fingers(24, ¶0034) on an upper surface of the package substrate(10);
a semiconductor chip(50, ¶0034) disposed on the upper surface of the package substrate(10), the semiconductor chip(50, ¶0034) having a first surface, and a second surface that is opposite to the first surface and faces the package substrate(10); and
a plurality of bonding wires(52, ¶0034) electrically connecting the semiconductor chip(50, ¶0034) and the plurality of bonding fingers(24, ¶0034),
wherein each of the plurality of bonding fingers(24, ¶0034) comprises:
a seed layer pattern(12, ¶0038) disposed on the upper surface of the package substrate(10), the seed layer pattern(12, ¶0038) having a first region(upper surface) and a second region(vertical side surfaces) surrounding the first region(upper surface);
a finger body(16, ¶0040) on the first region(upper surface) of the seed layer pattern(12, ¶0038) and having a predetermined thickness; and
a plating pattern(18,20, 22, ¶0041-43) covering an upper surface of the finger body(16, ¶0040) and contacting the second region(vertical side surfaces) of the seed layer pattern(12, ¶0038),
wherein a side surface of the plating pattern(18,20, 22, ¶0041-43) extends at an angle of 85-95 degrees(90°, Fig. 9) with respect to the upper surface of the seed layer pattern(12, ¶0038),
wherein a side surface of the seed layer pattern(12, ¶0038) is exposed by the plating pattern(18,20, 22, ¶0041-43), and wherein for each bonding finger(24, ¶0034) from the plurality of bonding fingers(24, ¶0034), one end of a bonding wire(52, ¶0034) from the plurality of bonding wires(52, ¶0034), is bonded to an upper surface of the plating pattern(18,20, 22, ¶0041-43).
Pun is not relied on to teach the semiconductor chip(50, ¶0034) having a first surface where chip pads are formed, a plurality of bonding wires(52, ¶0034) electrically connecting the chip pads and the plurality of bonding fingers(24, ¶0034).
Jung teaches a semiconductor package(Fig. 2) wherein the semiconductor chip(210, col. 3, lines 34-37) having a first surface where chip pads(210a, col. 2, line 54-col. 3, line 4) are formed, a plurality of bonding wires(212, col. 2, line 54-col. 3 , line 4) electrically connecting the chip pads(210a, col. 2, line 54-col. 3, line 4) and the plurality of bonding fingers(230, col. 2, line 54-col. 3, line 4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Pun, so that semiconductor chip having a first surface where chip pads are formed, a plurality of bonding wires electrically connecting the chip pads and the plurality of bonding fingers, as taught by Jung, in order to connect the active surface of the chip via the chip pads(col. 2, line 54-col. 3, line 4).
Claim 8 rejected under 35 U.S.C. 103 as being unpatentable over Pun et al. (US 2018/0102312 A1) and Jung et al. (US 6,333,252 B1) as applied to claim 1 above further in view of Di et al. (US 2021/0366875 A1).
Regarding claim 8, Pun, in view of Jung, teaches the semiconductor package of claim 1, wherein each of the plurality of bonding fingers(24, ¶0034) has a first width in a long side direction and a second width in a short side direction(inherent).
Pun and Jung are not relied on to teach the first width in the long side direction is 80 μm to 120 μm, and the second width in the short side direction is a length 20 μm to 40 μm. Pun does teach the second width in the short side direction is a length of 10 μm. Further Di teaches the area or first width x second width is optimized in accordance with the size of the wire bond(¶0064) in order to feed-up space for greater storage capacity without increasing the overall form factor of the semiconductor device(¶0063). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Pum so that the first width in the long side direction is 80 μm to 120 μm, and the second width in the short side direction is a length 20 μm to 40 μm, since it has been held that when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art. See MPEP 2144.05.
Allowable Subject Matter
Claim 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding dependent claim 10, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “a side surface of the seed layer pattern is exposed by the plating pattern.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park (US 2019/0252306 A1) Discloses a semiconductor package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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/LAURA M DYKES/Examiner, Art Unit 2892
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